CoreLink DMC-520 Dynamic Memory Controller for Enterprise

CoreLink DMC-520 Dynamic Memory Controller for Enterprise Image (View Larger CoreLink DMC-520 Dynamic Memory Controller for Enterprise Image)
The CoreLinkTM 500 series introduces the 5th generation, CoreLink DMC-520 Dynamic Memory Controller specifically designed to provide an optimal solution for enterprise applications including servers and network infrastructure. The CoreLink DMC-520 uses the AMBA® 5 CHI (Coherent Hub Interface) specification to connect directly to the CoreLink CCN-504 Cache Coherent Network. The CoreLink DMC-520 provides a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. Enterprise class RAS (Reliability, Availability and Serviceability) features such as ECC for x72 DRAM, TrustZone security and End-to-End QoS are integral components of this new memory controller. CoreLink DMC-520 uses the DFI interface to enable integration with industry standard PHYs.

CoreLink DMC-520 Dynamic Memory Controller

Optimized and efficient access to the DRAM is critical to the performance of any Enterprise SoC. As the number of processing elements on a chip increases so, the demand for data increases. As the DRAM technology has evolved to DDR4, the frequency of operation rises, but also the complexity of making best use of the DRAM increases. Managing the differing demands of multiple processing elements while trying to make optimum use of DRAM is the challenge faced by a Dynamic Memory Controller.

The CoreLink DMC-520 is ARM's fifth generation of Memory Controller. CoreLink DMC-520 has been designed to meet the needs of an Enterprise system based around a Cache Coherent Network product from ARM. CoreLink DMC-520 is a key part of ARM's End-to-End Quality of Service (QoS) scheme that includes features distributed across both Interconnect and Memory Controllers.

The CoreLink DMC-520 has an advanced QoS based scheduling and arbitration algorithm. QoS values defined by the system are used to re-order transitions to be sent to memory. The DMC arbitration uses bank and row status to aggressively re-order transactions to optimize both bank parallelism and in row hits.

The CoreLink DMC-520 has been specified, designed and validated in conjunction with ARM's CoreLink 500 System IP.

High bandwidth, low latency DMC-520

ARM has developed a DMC performance methodology against which to specify, design, develop and test Memory Controller performance. 

CoreLink DMC-520 achieves greater than 90 percent of theoretical maximum DRAM bandwidth across a wide range of test scenarios.

QoS mechanisms in CoreLink DMC-520 ensure critical masters can achieve minimum latency.

System Interfaces    1 for direct connection to CCN products using the AMBA® 5 CHI (Coherent Hub Interface) specification
System Data Width   128 bit
Configuration  Via APB interface
Memory Interfaces  1 Memory interface to connect to DRAM via DFI interface
Memory Types DDR3, DDR3(L) and DDR4
Memory Width  x72 bit DRAM
ECC SECDED or Enhanced ECC 
QoS QoS based scheduling algorithm, non-blocking paths to DRAM through CCN
Low Power All DRAM power modes supported and hierarchical clock gating throughout the DMC

Cortex Processors

CoreLink DMC-520 can be used to provide memory access in systems built around ARMs Cortex-A series processors.

CoreLink System IP

CoreLink DMC-520 is part of the CoreLink 500 series of System IP.  CoreLink DMC-520 is designed for direct connection to CoreLink CCN-504 Cache Coherent Network using the AMBA® 5 CHI (Coherent Hub Interface) specification.

Physical IP

ARM Artisan provide standard cell library and compiled RAM for implementation of CoreLink DMC-520. 


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