CoreLink Static Memory Controllers

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Static or Non-volatile memory is typically a shared resource to which many different masters and processes require access. Effective, error-free access to static memory is important for both system performance and system power.

The CoreLink™ Static Memory Controllers (SMC) provide efficient interfaces to a wide range of types of non-volatile memory, leveraging the features of AMBA AXI to schedule requests to the memory in the most optimal fashion. They are designed for compatibility with the ARM portfolio of Dynamic Memory ControllersInterconnect and processor solutions emphasizing low power and high performance operation.


Why choose a CoreLink Static Memory Controller?

Most systems with ARM processors will have off-chip static (non-volatile) memories. These will contain information such as object code and data files. System performance depends on being able to read and write this data efficiently and accurately.

CoreLink Static Memory Controllers are available for AMBA AXI (SMC-35X) and AMBA AHB (PL24X).  These controllers are optimized for the bus protocol and have been developed to complement the CoreLink Network Interconnect and Dynamic Memory Controllers along with ARM CPU and media processors.

Verification and Benchmarking

Understanding the performance and functionality of the memory controller in a system context is critical to the specification and development of the controller. The system level verification and benchmarking that we perform ensures that we deliver products that have been fully qualified alongside the cores and on-chip interconnect. These results then drive the specifications of both current and future memory controllers. They ensure our Partners have the efficient, low-risk, easy to integrate solutions that enable development to proceed smoothly - meeting performance goals and delivering time to market.

And for the future?

ARM is committed to ensuring the ARM ecosystem has the memory controller solutions our Partners require. We participate in the industry standards bodies defining new memory interfaces to ensure that they meet the needs of our Partners. Collaboration with ARM teams developing new cores and new interconnects ensures that memory interface support for new products is available to our partners when they need it.

AXI Static Memory Controllers

The SMC-35X family of products provide an interface between AXI interconnects and a range of non-volatile memories. 

The SMC-35X has a wide range of configurable parameters, these are described under the specifications tab.

Product  Non-Volatile Memory Supported  Notes
 SMC-351  NAND Flash up to 4 chip selects
 SMC-352  NOR Flash / SRAM up to 4 chip selects
 SMC-353  NAND Flash and NOR Flash / SRAM up to 4 NAND and 4 NOR/SRAM
 SMC-354  NOR Flash / SRAM up to 8 chip selects in 2 groups of 4

AHB Memory Controllers

The PL24X family products provide an interface between AHB interconnects and non-volatile memory. These are hybrid controllers also providing an interface to DRAM memory systems.

Product  NV Memory Supported  DRAM Support  AHB Ports





















Other combinations of memory can be supported by using a combination of the NIC-301 interconnect product with DMC-34X and SMC-35X memory controllers.

About the SMC-35X family of NAND Flash, NOR Flash and SRAM Controllers

The SMC-35X family is AMBA-compliant System-on-Chip (SoC) peripherals.

SMC-350 System Context

The product range consists of high-performance, area-optimized SRAM and NAND memory controllers with on-chip bus interfaces that conform to the AMBA AXI protocol. The product range consists of a number of controllers that support either one or two memory interfaces of type NAND or SRAM. The controllers are:

The NAND memory interface supports NAND flash with multiplexed Address/Data (A/D) buses.

The SRAM memory interface supports: 

  • Synchronous or asynchronous SRAM
  • Pseudo Static Random Access Memory (PSRAM)
  • NOR flash
  • NAND flash devices with an SRAM interface. 

Key Features

  • Configurable through AMBA Designer to support a wide range of memory and AXI bus widths.
  • Configurable command, read and write FIFO depths.
  • Optional 2-bit detect, 1-bit correct ECC.
  • Programmable to support a wide range of memory timing and command options for the widest range of device support.
  • Support for multiple clock domains, synchronous and asynchronous operation.

For further details on specifications, please refer to the Technical Reference Manual (TRM) linked from the Resources tab.


The SMC-35X and PL24X static and hybrid memory controllers are designed for compatibility with the ARM IP product portfolio.

 CoreLink SMC Products

 Related ARM IP Products


Static Memory Controllers
(SMC-341, SMC-342, SMC-343, SMC-343, PL241, PL242, PL243, PL244, PL245)

Dynamic Memory Controllers: DMC-340, DMC-341 and DMC-342 Complementary dynamic memory controllers
NIC-301QoS-301and ADK Interconnect for AMBA AXI for AHB systems
Level 2 Cache Controller L2C-310, DMA Controller DMA-330 System controllers
AMBA Designer For configuration and stitching.
VPE For performance exploration and functional verification
Cortex-A, Cortex-RARM11 and ARM9 CPU processors
Mali Graphics Processors and Video Engines Multimedia processors


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