Chinese

Japanese

About ARM

Forums

Events

News

Employment

Investors

	MARKETS		PRODUCTS & SOLUTIONS		CONNECTED COMMUNITY		TECHNICAL SUPPORT		DOCUMENTATION


		Technical Support


		Home Page

		Obtaining Support

		FAQs


		Development Tool FAQs


		IP FAQs


		Embedded Software FAQs


		Artisan Physical IP FAQs (Login Required)


		Downloads

		Documentation

		Training

		Where To Buy

		Keil MCU Tools

		What's New

		ARM Newsgroups




(Advanced Search) FAQs Documentation Downloads Forums

AMBA

To find information on a particular area, simply expand the relevant section.
To expand/collapse all areas simply click on the appropriate button below:

For further information you can use our 'Technical Support Search' facility at the bottom of this page.

AMBA 2 AHB - Arbitration

Arbitration: Can a master deassert HLOCK during a burst?

Arbitration: Can a master perform transfers other than IDLE when the bus was granted to it, but not requested by the master?

Arbitration: If a master is currently granted the bus by default, how many cycles before starting an non-IDLE transfer does it have to assert HBUSREQ?

Arbitration: What is the relationship between the HLOCK signal and the HMASTLOCK signal?

Arbitration: When can the HGRANT signal change?

Arbitration: Why is HADDR sometimes shown as an input to the arbiter?

Can an arbiter be designed to always allow bursts to complete?

When should a master assert and deassert the HLOCK signal for a locked transfer?

When should a master deassert its HBUSREQ signal?

When will the arbiter grant another master after a locked transfer?

AMBA 2 AHB - General

General : What system support is required if a slave can be powered down or have its clock stopped?

General : When can Early Burst Termination occur

General: Can HTRANS change whilst HREADY is low?

General: Can a BUSY transfer occur at the end of a burst?

General: Can a master change the address/control signals during a waited transfer?

General: Can an AHB master be connected directly to an AHB slave?

General: Do all slaves have to support the BUSY transfer type?

General: Does the address have to be aligned, even for IDLE transfers?

General: How many masters can there be in an AHB system?

General: How should AHB to APB bridges handle accesses that are not 32-bits?

General: Is HREADY an input or an output from slaves?

General: Is a default slave really necessary?

General: Is a dummy master really necessary?

General: Is it legal for a master to change HADDR when a transfer is extended?

General: Is it specified that HPROT, HSIZE and HWRITE remain constant throughout a burst?

General: The specification recommends that only 16 wait states are used. What should you do if more than 16 cycles are needed?

General: What are the different bursts used for?

General: What default state should be used for the HREADY and HRESP outputs from a slave?

General: What is a default slave?

General: What is the difference between a dummy bus master and a default bus master?

General: What is the recommended default value for HPROT?

General: What is the state of the AHB signals during reset?

General: What sequences of transfers types (HTRANS) can occur on the bus?

General: When a master rebuilds a burst which has been terminated early are there any limitations on how it rebuilds the burst?

General: Why is a burst not allowed to cross a 1 kilobyte boundary?

How do you connect an AHB Master to an AHB-lite system?

How do you connect an AHB slave to an AHB-lite system?

How do you connect an AHB-lite Master to a full AHB system?

How do you connect an AHB-lite Slave to a full AHB system?

How does AHB differ from AHB-lite?

How many clock cycles should the reset signal in an AMBA system be asserted for?

AMBA 2 AHB - Split/Retry

How does the AHB handle LOCKed SPLITs?

Split/Retry: Can a SPLIT or RETRY response be given at any point during a burst?

Split/Retry: Can a slave assert HSPLITx in the same cycle that it gives a SPLIT response?

Split/Retry: Can a slave use both SPLIT and RETRY responses?

Split/Retry: Do all masters have to support SPLIT and RETRY?

Split/Retry: Do all slaves have to support the SPLIT and RETRY responses?

Split/Retry: What address should be on the bus during the IDLE cycle after a SPLIT or RETRY?

Split/Retry: What is the difference between SPLIT and RETRY responses?

Split/Retry: What value should be used for HTRANS when an AHB master gets a RETRY response from a slave in the middle of burst?

Split/Retry: Will a master always lose the bus after a SPLIT response?

AMBA 2 APB - General

General: How should AHB to APB bridges handle accesses that are not 32-bits?

General: Why is there no wait signal on the APB?

How many clock cycles should the reset signal in an AMBA system be asserted for?

AMBA 3 AXI - Atomic

Are there any issues with exclusive accesses passing from one width of data bus to another?

Are there any recommendations about the types of accesses that are used for atomic accesses?

Can a master change the control signals for different transactions in a locked sequence?

Can an exclusive access use sparse write data strobes?

Can an unlocking transaction be an exclusive access?

Does a master always have to perform the write portion of an exclusive access?

How does a SWP operation on a CPU translate in to bus activity?

How important is it that a sequence of locked transactions does not cross a 4k byte boundary?

When a master has issued a locked transfer with one ID can it start a different locked transfer with a different ID?

AMBA 3 AXI - Control

How do you calculate addresses used in WRAP type bursts?

How should a 32-bit write accesses across a 64-bit bus be represented as AXI transactions?

Should the protection/cache information for address regions be consistent between read and write operations?

The specification mentions that AxPROT[2] information is just a hint. Is the information given by the other AxPROT bits always accurate?

What are the allowable byte lane strobes for fixed address burst?

Why are the read and write address buses defined with all four bits of ACACHE. Does a read transaction need to give the write allocate information and vice versa?

AMBA 3 AXI - Handshake

At what point can the master consider that the transaction has been accepted by the slave such that the responsibility for hazard checking lies with the slave?

What happens if the slave is keeping AWREADY low waiting for the write response to be accepted while the master is keeping BREADY low waiting for the address to be accepted by the slave?

What is meant by the arrows in section 3.3, "Dependencies between the channel handshake signals"?

Why is the READY signal not sticky?

Why is the VALID signal described as "sticky"?

Why is the VALID signal sticky?

AMBA 3 AXI - Miscellaneous

Are there any recommendations for verifying AXI components?

How do you ensure interoperability between AXI components?

What is the ACLKEN signal ?

When an interconnect adds bits to the ID field does it add high-order bits or low-order bits?

AMBA 3 AXI - Ordering

Are there any issues related to hazard detection on overlapping locations?

Can the WVALID signal for a write transfer be active before the AWVALID? If so, how does the interconnect know which slave the transfer is for?

Can write responses be re-ordered in the same way that read data can be re-ordered?

If a slave receives three addresses from different masters M1, M2 and M3 in that order and has an interleaving depth of 3 can the slave expect to see any data from M3 before it sees data from masters M1 and M2?

Should slaves/bridges which have some form of write buffer capability also include forwarding logic to return the result of a read transaction when a write to the same location is stored in the write buffer?

When can a master consider a write transaction complete, when it is trying to determine which write data sources it can interleave?

When there are several bursts with same ID to a slave, are they counted separately or as one in regard to the write data interleaving-depth of the slave?

AMBA 3 AXI - Responses

How should a bridge deal with an AXI transfer that is marked as non-secure and bufferable?

If BRESP indicates an error, does that mean that none of the transaction’s data was written to memory?

Should a slave respond with an error or OKAY response when the user addresses memory space in the slave that has no registers?

What AXI response value should be given by a slave which contains a mixture of secure and non-secure registers, when a non-secure access is attempted to a secure register?

What AXI response value should be given to a non-secure access to a secure address location?

To download a single page of AMBA FAQs specific to the Area(s) you are interested in, please click on the 'Merge FAQs' button below. On the page that follows you will be prompted to select which Area(s) you wish to be included in your customized list of FAQs.

Back to FAQs index

Other ARM Websites | Help with Accessibility

Glossary | Sitemap | Help

LEGAL STATEMENT