[System FPGA build 4, ispClock5620 'Master' build 1, 'Slave' build 2, Config PLD build 0] FPGA, PLD and iSPClock 5620 configuration binary images for the PB1176JZF-S baseboard. The PB1176JZF-S has some programmable logic on-board (one FPGA, three PLDs and two ispClock 5620 devices). This zip file contains the latest and previous builds of the binary configuration images for the FPGA, Config PLD and ispClock ICs. Note: The zip file does not contain the Progcards utility that must be used to reprogram the FPGAs and PLDs. The latest version of Progcards must be downloaded separately and combined with these boardfiles to effect the full programming solution. Note that upgrading the System FPGA to build 4 will cause a change in behavior of the DIP switches, S7. Please refer to RevB of the PB1176JZF-S user guide for the new switch assignments. Please refer to the documentation area of the ARM website: Boards User Guides
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