[Updated 7 Feb 2007] Most Core Tiles have one programmable logic part on board (a PLD), which is used to control many of the board's configuration options such as power supply voltages, clock routing and test chip static configuration signals. Some Core Tiles also use PLL chips which have non-volatile storage for timing parameters. Under normal circumstances, it should not be necessary to re-program the PLD or ISPClock PLLs on a Core Tile, since they are programmed during manufacture and do not need to be modified by the end user. The only reason it should need re-programming is if it becomes corrupted, or if ARM releases an updated image for the device. This zip file contains both the latest and previous builds of the binary configuration images for these boards. The zip files do not contain the Progcards utility that must be used to reprogram the devices. The latest version of Progcards must be downloaded separately and combined with the boardfiles to effect the full programming solution. Similarly, the revision history document for boardfiles is no longer included in the zipfile, but can be downloaded separately. For more information about issues when reprogramming Versatile boards, see the Versatile FAQs in the ARM Technical Support pages. Note that Core Tiles cannot be operated stand-alone, since they have no built-in clock source, and no power supply or JTAG connections on-board.
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