Artisan DDR PHY Solutions

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ARM® DDR Interface IP delivers a comprehensive timing solution for a broad range memory sub-systems ranging from high-speed mission critical applications to low-power memory sub-systems. These robust silicon-proven interfaces have been optimized to provide the highest bandwidth at the lowest power and area.



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DDR PHY solutions provide standards based high-speed parallel interface physical solutions meeting key industry standards such as DDR3, DDR2, LPDDR and LPDDR2. Artisan DDR PHY solutions are foundry and process optimized delivering market leading performance, power and area.

ARM Artisan DDR PHY Key Benefits

  • Comprehensive memory interface solutions for ARM based SoC in conjunction with ARM Corelink family of memory controllers
  • Ensures the highest bandwidth, lowest latency and lowest power configuration without sacrificing flexibility in implementation
  • Provides a Time To Market advantage leveraging mature architecture and silicon proven technology
  • Lowest risk solutions with a long history of high volume production backed by an experienced support team.

The ARM DDR memory interface IP offers a comprehensive solution for a broad range of application from LPDDR to DDR3. Targeting data rates from 100Mbps up to 1.6 Gb/s data rates, the ARM DDR Interface IP offers the best Power/Performance solution for SoC and ensure robust operation in various packaging and system configurations. The PHY comprises of all analog and digital block required to build the DDR interface. ARM reduces your design risk and ensures seamless integration between blocks and rest of the system.

The DDR interface comes designed to cope with wide range of voltage, temperature, process, package and system variations while ensuring robust signaling between the SoC and off-chip memories. It includes on-die compensation circuitry and supply decoupling to increase power supply noise immunity and reduce jitter.

The ARM DDR interface IP is no stranger to Low Power, deployment of low power operation goes from SoC level all the way down to individual circuit level. Various low power techniques, combined with traffic aware interface, can yield in a significant reduction to the DDR interface power.

  • Compliant to JEDEC Standards (DDR, DDR2, LPDDR, DDR3)
  • Operating speed up to 1.6Gbps
  • Tight skew specs & Minimum propagation delays
  • Area optimized to reduce chip size
  • Robust ESD structures 2000V HBM and 200V MM

  • Multiple Standard support LPDDR, LPDDR2, DDR2 and DDR3
  • Seamless interoperability between IP
  • Adjustable slew rates & drive strengths
  • Low latency with programmable timings
  • Robust ESD enabling full speed designs
  • PVT compensation and timing calibration
  • At speed testability
  • Low jitter with superior noise rejection

ARM DDR PHY and I/O Interface IP may be used in complex SoC designs which require many types of IP across the design. In addition to DDR PHY and I/O IP, ARM offers a wide variety of compatible Processor to Pads IP including ARM Processor, Multimedia, System and Physical IP, with which to develop your SoC.

Visit DesignStart to find ARM IP solutions for your SoC and start designing today.
ARM Physical IP   ARM Processor IP   ARM System IP   ARM Multimedia IP  
General Purpose I/O Cortex-A9 Memory Controllers Mali-400
Specialty I/O Cortex-A5 System Controllers Mali-200
Logic Cortex-R4 Peripherals Mali-VE6
Embedded Memory  Cortex-M3 Debug & Trace Mali-VE3

You may view ARM DDR and other Physical IP products in DesignStart. Registered users of DesignStart can download Front-End Packages for all products that enable a comprehensive IP evaluation including place and route. DesignStart also includes access to technical documentation, including Datasheets and Application Notes.

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