SNUG 2013 - Santa Clara
Venue:
Santa Clara Convention Center
Location:
Santa Clara, CA
Date:
25 March 2013
Room/Booth/Stand:
IP Community
Visit ARM at SNUG 2013 to learn how we enable chip designers to innovate continuously using our integrated silicon-proven system design IP. ARM provides a total system solution for your SoC through integrated and optimized software, CPU, GPU, and system and physical IP, tuned to a specific manufacturing process and supported by the largest eco-system of partners in the industry. This holistic design solution provides proven design advantages and reduces your overall time –to-market design cycle.
As the consumer demand for feature rich electronic devices continues to push the envelope of performance and power, semiconductor and electronics companies face growing design challenges. These include addressing the complexity of integrating hardware and software in advanced SoCs in a timely and cost-effective manner. Solving these challenges requires design collaboration from the leading companies of the design chain including foundries, processor architecture, tools, software and third party IP providers. ARM has established strategic design engagements with these leading companies to enable rapid development of low-power, high performance SoCs.
Visit the ARM booth located in the IP Community. To learn more about SNUG 2013 click HERE.
Monday, March 25, 2013
| ARM Sponsored Sessions | |||
| Time | Title / Topic | Speaker | Location |
|---|---|---|---|
| 10:00 - 12:30 pm | Routing at 20nm - It is Challenging but Achievable | Chad Hale, Principal Design Engineer, ARM | MA 02 |
This paper describes some of the routing challenges at 20nm and the need for close collaboration between foundry, IP provider and EDA tools. Design rule complexity has increased significantly since the days of simple space and width rules. This paper will dive deep at a few of the new 20nm routing rules and how coding them incorrectly will significantly impact DRCs and run time of a design. It will look at evaluating DFM rules and determining which ones to include. This paper will also discuss how routing rules are implemented and verified. It will also cover why the VIA definitions have increased exponentially over previous nodes. While some of the rules are yet to be supported in ICC, several techniques were used to address these challenges. It concludes with best practices and results in terms of the violations seen in ICC and correlation with signoff verification across different test vehicles.
Synopsys Tools Used: IC Compiler
Target Audience: Engineers facing 20nm routing challenges - Advanced
Tuesday, March 26, 2013
| ARM Sponsored Sessions | |||
| Time | Title / Topic | Speaker | Location |
|---|---|---|---|
| 3:45 - 5:15 pm | Advanced Retention Power Gating: Unlocking Opportunisitc Leakage Savings in High Performance Mobile SoCs | John Biggs - SR. Principal Engineer, David Flynn - Fellow, James Myers - Staff Engineer, ARM | TC01 TC1 A |
Power gating is now a mainstream leakage mitigation technique in all modern applications processor cores, but saving away program state and actually shutting down is an energy gamble left to the operating system. A more energy optimal approach is to use hardware state retention registers but the associated area and performance penalties have prevented wide adoption to date. This paper describes an advanced state retention scheme which builds upon power gating with minimal additional area and performance impact, discusses application to an ARM processor implemented using Design Compiler and IC Compiler tools with a UPF-based flow and 28nm library.
Synopsys Tools Used: Design Compiler, IC Compiler, VCS, PrimeTime-PX
Target Audience: Implementation engineers with knowledge of low-power design, multi-voltage tools and power intent, and anyone interested in low-power chip design - Intermediate
