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SNUG - Silicon Valley 2014

Venue:

Santa Clara Convention Center

Location:

Santa Clara, CA

Date:

24 March 2014 - 26 March 2014

Room/Booth/Stand:

 


SNUG Silicon Valley 2014
March 24, 2014 – March 26, 2014

Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, CA 95054

Visit ARM at SNUG 2014 to learn how we enable chip designers to innovate continuously using our integrated silicon-proven system design IP. ARM provides a total system solution for your SoC through integrated and optimized software, CPU, GPU, and system and physical IP, tuned to a specific manufacturing process and supported by the largest eco-system of partners in the industry. This holistic design solution provides proven design advantages and reduces your overall time –to-market design cycle.

As the consumer demand for feature rich electronic devices continues to push the envelope of performance and power, semiconductor and electronics companies face growing design challenges. These include addressing the complexity of integrating hardware and software in advanced SoCs in a timely and cost-effective manner. Solving these challenges requires design collaboration from the leading companies of the design chain including foundries, processor architecture, tools, software and third party IP providers. ARM has established strategic design engagements with these leading companies to enable rapid development of low-power, high performance SoCs.

Visit the ARM booths, located in the Designer Community and the Prototyping and System Design Expo area.

To learn more about SNUG 2014 click here


Please attend the following sessions with speakers from ARM:

Monday March 24, 2014

Time Title / Topic Speaker Description
11:00 am - 12:30 pm MA-04 Circuit Simulation
CustomSim-Based Comprehensive EM/IR Analysis, Visualization, and Violation Correction

Sateesh Chandramohan, Prashant Lokeshwar - ARM
Danny Cheng, Darren Hsu - Synopsys, Inc.

Shrinking geometries and higher clock frequencies have made IR Drop and Electromigration (EM) analysis a critical sign-off step. In this paper we discuss the use model of CustomSim's Native Reliability Analysis features to perform EM/IR analysis. We also discuss how the integrated environment of CustomSim RA and CustomSim RA Viewer analyze, visualize, and fix the violations. This paper also describes possible automation from the analysis stage to violation corrections.

Tuesday March 25, 2014

Time Title / Topic Speaker Description
10:30 am - 12:00 pm TA-07 Signoff- FinFET & Process Variation Panel
The "Real World" Weighs in on FinFET and Process Variation Impact

Brian Cline - ARM
Glen McDonnell - Broadcom
Tom Quan - TSMC
Susan Wu – Xilinx
Bari Biswas - Synopsys, Inc.

Over the past several years, the semiconductor industry has been preparing for the arrival of FinFET technology, which has promised to deliver higher performing, lower power devices at densities that allow unprecedented functionality to be designed into a single IC. The challenges have been well documented and innovative solutions have been proposed by foundries, EDA vendors, and designers, but where do we stand today? Have the technology challenges been addressed, are the design and analysis tools meeting expectations, and has the potential of FinFET truly been harnessed? In this panel discussion, hear industry experts on the forefront of innovation evaluate the reality of the FinFET promise. Panelists will discuss their hands-on experiences in the areas of process technology, parasitic modeling, variation modeling, timing signoff analysis, and IP and design development. Highlights will include real design experience with increased process variation and a solution to remedy these effects.
1:30 - 3:30 pm

TB-10 Systems
Application of Virtual Prototypes, Current and Future

Robert Kaye - ARM

The last few years have seen a rapid growth of virtual prototypes, abstract simulation models used by SoC software developers. There are many factors driving this growth, including maturing technology, increased business pressure, and changing software development paradigms. In this presentation we will explore the underlying technology that enables virtual prototype development and deployment at all stages of the SoC design process with Synopsys Virtualizer and VDK tools and models. This will be illustrated through a range of different real-world use cases and user experiences. Finally, we will look at the future of virtual prototypes: what are the challenges and how are these being addressed? What trends are driving new requirements and functionality, what new use cases could these developments unlock, and how will the technology evolve in the near- to mid-term?

Click here to view the complete agenda




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