CoreLink CCN-504 Cache Coherent Network

CoreLink CCN-504 Cache Coherent Network Image (View Larger CoreLink CCN-504 Cache Coherent Network Image)
The ARM® CoreLink™ CCN-504 Cache Coherent Network offers scaling to 16 processor cores to give system architects an optimal solution for enterprise applications including servers and network infrastructure. The significant increase in data over the next 10-15 years demands more energy-efficiency, and ARM has the Cortex processor and CoreLink System IP to provide a solution.

CoreLink CCN-504 can deliver up to one Terabit of usable system bandwidth per second. It will enable designers to provide high-performance, cache coherent interconnect for ‘many-core’ enterprise solutions built using the ARM Cortex™-A15 MPCore™ processor and the latest ARM Cortex-A50 series processors with 64-bit support. 


CoreLink CCN-504 Introduction

CoreLink CCN-504 is the first in a family of products.  It enables a fully-coherent, high-performance many-core solution that supports up to 16 cores on the same silicon die. The CoreLink CCN-504 enables system coherency in heterogeneous multicore and multi-cluster CPU/GPU systems, such as those required for the networking and high-performance computation markets, by enabling each processor in the system to access the other processor caches. This reduces the need to access off-chip memory, saving time and energy, which is a key enabler in systems based  on ARM big.LITTLE™ processing, a new paradigm that can deliver both high-performance, required for content creation and consumption, while also delivering extreme power efficiency for extended battery life.

Optimised for ARM Cortex Processors

The CoreLink CCN-504 supports both the current-generation high-end Cortex-A15 processor and the latest Cortex-A50 series processors and is the first in a family of network-based interconnect products planned by ARM. Building on the success of AMBA® 4 ACE™ specification the CoreLink CCN-504 also benefits from ARM experience in hardware-based coherency, that enables improved energy-efficiency and lower latency than software coherency. Over 8000 AMBA 4 ACE specifications have been downloaded to date.

Integrated Low Latency Level 3 Cache

The CoreLink CCN-504 Cache Coherent Network includes integrated level 3 (L3) cache and snoop filter functions. The L3 cache, which is configurable up to 16MB, extends on-chip caching for demanding workloads and offers low latency on-chip memory for allocation and sharing of data between processors, high-speed IO interfaces and accelerators. The snoop filter removes the need for broadcast coherency messaging, further reducing latency and power.

High Performance DDR3 and DDR4 Memory Interfaces

The CoreLink CCN-504 is optimised to work with the CoreLink DMC-520 Dynamic Memory Controller. The CoreLink DMC-520 provides a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. Enterprise class RAS (Reliability, Availability and Serviceability) features such as ECC for x72 DRAM, TrustZone security and End to End QoS are integral components of this new memory controller. CoreLink DMC-520 is part of an integrated ARM DDR4/3 interface solution incorporating Artisan® DDR4/3 Phy IP planned for introduction in 2013.

CoreLink CCN Cache Coherent Network Series

CoreLink CCN-504 Cache Coherent Network is the first in a series of products designed for high performance, power efficient server and network infrastructure products. ARM will be announcing further products to allow our partners to optimise the interconnect for their system requirements.

ARM leadership in scalable, power-efficient multi-core and ‘many-core’ technology will address the demand for energy-efficient SoC solutions for use in servers and network infrastructure. As these markets are increasingly power- and cost-constrained, the effectiveness of these ‘many-core’ processor clusters rely on the whole system being optimized.


Bandwidth and Latency

CoreLink CCN-504 Cache Coherent Network can deliver up to one Terabit per second of usable system bandwidth. It will enable designers to provide high-performance, hardware managed cache coherency between processor clusters and IO interfaces and accelerators.

Bandwidth to the dual channel DDR4 memory approaches 50GB/s.


CoreLink CCN-504 is designed to work closely with the latest ARM Cortex applications processors and can be imlemented at clock speeds approaching that of the Cortex-A15 or Cortex-A57 processor. Interfaces to memory and processors can be configured for asynchronous interfaces to allow power management including dynamic voltage and frequency scaling.


High Performance, Efficient Coherent Network 

CCN-504 Specification

Performance Usable system bandwidth: ~ 1 Terabit/second Frequency: Up to CPU frequency
CPUs supported Cortex-A15 and next-generation ARMv8 processors
Bus Width 128 bits
Scalability Up to 16 cores (4 coherent clusters)
Level 3 cache Integrated, configurable 8-16MB
Snoop Directory Integrated to minimize snoop broadcast
Low Power Support Extensive clock gating, leakage mitigation hooks Granular DVFS and CPU shutdown support Partial or full level-3 cache shutdown Retention modes

Scalable System Features


IO Coherency support for up to 18 ports AMBA 4 AXI4/ACE-Lite interfaces supported in addition to CPU and DMC ports 

DDR 2 channels supported with CoreLink DMC-520
RAS ECC on RAMs and parity on transport
QoS Integrated QoS regulation and priority management
Security TrustZone® aware

Cortex Processors

CoreLink CCN-504 offers hardware coherent ‘many-core’ enterprise solutions built using the ARM Cortex™-A15 MPCore™ processor and the latest Cortex-A50 series processors.

CoreLink System IP

CoreLink CCN-504 is one part of a system solution available from ARM including:

Graphics Processors

ARM Mali™ Graphics Processors including Mali-T600 series of GPUs can be connected to the ACE-Lite interfaces of CoreLink CCN-504 to provide hardware IO Coherent graphics acceleration.

Physical IP

ARM Artisan® provide standard cell library and compiled RAM for implemenation of CoreLink CCN-504. In addition the CoreLink DMC-520 Dynamic Memory Controller ARM Artisan DDR4/3 Phy interface provide an integrated memory solution.


Press release:

ARM Announces New High-Performance System IP to Address Demand for Energy-Efficient ‘Many-core’ Solutions for the Enterprise Market

Public licensees:

LSI, a leading designer of intelligent semiconductors that accelerate storage, mobile networking and client computing, and Calxeda, an innovative supplier of disruptive SoC technology for the server market, are lead licensees for the CoreLink CCN-504 launch.

“Calxeda and ARM have been working closely to meet the demands of the datacenter since ARM's initial investment in our company in 2008, and we are beginning to see the fruits that relationship,” said Barry Evans, co-founder and CEO, Calxeda. “We are already building our next generation datacenter-class solutions using this new ARM CoreLink technology, and think we will once again send shockwaves across the industry when they are announced.”

“To meet the demands of rapidly growing mobile network traffic, LSI and ARM have worked closely to drive a feature-rich on-chip interconnect that can serve as the backbone for industry-leading many-core system-on-chip devices,” said Gene Scuteri, vice president of engineering, LSI. “ARM expertise in processor and interconnect technology, guided by LSI's deep understanding of networking and compute workloads, has delivered a robust, carrier-grade interconnect that will deliver scalable, deterministic performance and quality of service for today’s most advanced networks.”


Please contact ARM for more information.