The ARM Cortex™-A series of applications processors provide an entire range of solutions for devices hosting a rich OS platform and user applications ranging from ultra-low-cost handset through smartphones, mobile computing platforms, digital TV and set-top boxes through enterprise networking, printers and server solutions. The high-performance Cortex-A15, the scalable Cortex-A9, the market-proven Cortex-A8 processor, and the high-efficiency Cortex-A7 and Cortex-A5 processors all share the same architecture and therefore full application compatibility, that includes support for the traditional ARM, Thumb® and high performance and compact Thumb-2 instruction sets.
The Cortex-A15 and Cortex-A7 both support an extension to the ARMv7A architecture that brings support for large physical address reach and hardware virtualization, as well as AMBA4 ACE coherency. Together, these enable big.LITTLE processing.
Cortex-A processors, used in applications that have high-compute requirements, run rich operating systems and deliver interactive media and graphics experience from the latest technological mobile internet must-have devices such as handsets and ultra-portable netbooks or SmartBooks, to automotive infotainment systems and next generation digital TV systems.
Cortex-A processors are geared towards providing the full internet experience, but are used in a wide variety of applications including:
|Computing||Netbook, Smartbook, Tablet, eReader, Thin client|
|Mobile Handset||Smartphones, Feature phones|
|Digital Home||Set-top Box, Digital TV, Blu-Ray player, Gaming consoles|
|Enterprise||Laserjet printers, routers, wireless base-stations, VOIP phones and equipment|
|Wiresless Infrastructure||Web 2.0, wireless base stations, switches, servers|
The success of the Cortex-A processors is built on the success of our partners who have licensed these processors and developed a wide array of success stories in various markets.
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The Cortex-A7 and Cortex-A15 extend multi-core coherence beyond the 1~4 core cluster with AMBA4 ACE (AMBA Coherency Extension)
The Cortex-A5, Cortex-A7, Cortex-A8, Cortex-A9 and the Cortex-A15 processors are all used in a wide variety of performance applications. However while all support the same excellent base capabilities and full software compatibility, the processors offer significantly different characteristics to ensure the right-fit for tomorrow's advanced embedded solutions.
All Cortex-A Processors share a common architecture and feature set. This makes them the best solution for open platform design where compatibility and portability of software between design is of upmost importance:
Together, the range of Cortex-A processor provide design flexibility by providing the required peak performance points and scalability and delivering the desired power efficiency and silicon cost while maintaining full software compatibility.
|Core||Cortex-A5||Cortex-A5 MPCore||Cortex-A8||Cortex-A9||Cortex-A9 MPCore||Cortex-A9|
|Cortex-A15 MPCore||Cortex-A7 MPCore|
|Architecture||ARMv7||ARMv7 + MP||ARMv7||ARMv7||ARMv7 + MP||ARMv7 + MP||ARMv7|
|GIC-390||Integrated- GIC||GIC-390||GIC-390||Integrated- GIC||Integrated- GIC||Integrated-GIC||GIC-400|
|300-800 MHz||300-800 MHz||600-1000 MHz||600-1000 MHz||600-1000 MHz||800-2000 MHz||1000-2500 MHz||800-1500MHz|
|DMIPS/MHz||1.6||1.6 per CPU||2.0||2.5||2.5 per CPU||5.0 (dualcore)||TBC||1.9 per CPU|
The Cortex-A9 processor is available as either a single-core or 1-4 core multicore synthesisable processor each offering 2.5 Dhrystone MIPS per MHz per CPU. In its single-core implementation an area optimized implementation of the processor provide a minimal footprint and exceptional energy efficiency for traditional embedded designs, while a speed optimized multicore implementation offers up to four time the total performance with the additional advantages of cache coherence, integrated peripherals and advanced bus interface options.
A dual-core multicore solution is also available as a hard macro which can achieve over 2 GHz typical performance having leveraged the ARM high performance Physical IP within its implementation.
The Cortex-A9 has also been hardened to the TSMC 40G/GL process as a fully configured dual-core hardmacro. Offering performance over 2GHz when selected from typical silicon. These macro provide the silicon manufacturer a low-risk, and accellerated path to delivering the ARM low power solution for various high performance markets.
The Cortex-A8 processor is a dual-issue, in-order superscalar processor offering 2.0 Dhrystone MIPS per MHz targetted at highly optimized, power-efficient implementations that deliver the high-level performance required for a traditional single-processor based devices. The Cortex-A8 has established the ARMv7 architecture in the marketplace and is already available in diverse applications including smartphones, smartbooks, portable media players and other consumer and enterprise platforms.
The Cortex-A5 processor is the smallest, lowest power ARM multicore processor capable of delivering the Internet to the widest possible range of devices: from ultra low cost handsets, feature phones and smart mobile devices, to pervasive embedded, consumer and industrial devices.The Cortex-A5 processor is fully application compatible with the Cortex-A8, Cortex-A9, and Cortex-A15 processors, enabling immediate access to an established developer and software ecosystem including Android, Adobe Flash, Java Platform Standard Edition (Java SE), JavaFX, Linux, Microsoft Windows Embedded, Symbian and Ubuntu.
The Cortex-A7 processor is similar in power and area to the ultra-efficient Cortex-A5, but brings a 15~20% performance increase as well as full architectural compatibility with the high-end Cortex-A15 CPU, including large physical address extensions (LPAE), hardware virtualization support, and AMBA4 ACE (AMBA Coherency Extension). The small and power efficient Cortex-A7 is ideal for the latest low-cost smartphone and tablet applications as a standalone CPU, and can be combined with the Cortex-A15 in a big.LITTLE processing configuration.
The Cortex-A processors share a number of key technologies that make them ideal for portable media-rich devices.
|RISC Processor Core||Instruction Set Architecture|
|Media Acceleration||Multicore Technologies|
|Advanced Memory System||System Extensions|
The ARM MPCore technology allows for design-configurable processors supporting between one, two, three or four CPUs in operate in an integrated cache coherent manner. These multicore processor clusters are fully coherent at the level-1 cache boundaries and in addition can be configured to extend limited coherency into the rest of the System on a Chip (SoC) through an Accelerator Coherence Port (ACP). The ACP permits system-mastering peripherals and accelerators with a non-cached view of memory, such as a DMA engine or cryptographic accelerator core, to share the processor caches in a fully cache coherent manner. The multicore cluster includes a Global Interrupt Controller (GIC) architecture compliant integrated interrupt and communication system with private peripherals for increased performance and simplified software portability. This GIC can be configured to support between 0 (legacy bypass mode) to 224 independent interrupt sources providing a low latency interrupt path to a large number of devices. The processor can support either a single or dual 64-bit AMBA® 3 AXI™ interconnect interface with the option for full speed filtering between different address space within the SoC.
The intelligence of the MPCore technology comes from the Snoop Control Unit (SCU) which is responsible for managing the interconnect, arbitration, communication, cache-2-cache and system memory transfers, cache coherence and other multicore capabilities for all MPCore technology enabled processors.
ARM MPCore technology allows for very efficient, scalable multi-processing CPU clusters which give a very high-range of performance possibilities with very low software overhead. In Symmetric Multi-Processing (SMP) mode, the OS scheduler handles all allocation of threads to the processing cluster making it transparent to applications running. Most current high-level operating systems have built-in support for this mode of operation.