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Cortex-R5 Processor

Cortex-R5 Processor Image (View Larger Cortex-R5 Processor Image)
The ARM® Cortex®-R5 processor provides a high performance solution for real-time applications in markets including mobile baseband, automotive, mass storage, industrial and medical. The processor, based on the ARMv7R architecture, provides a simple migration path from the Cortex-R4 processor, and onwards to the higher performance Cortex-R7 processor.

The Cortex-R5 processor extends the feature set of the Cortex-R4 processor to enable higher levels of system performance, increased efficiency and reliability, and enhanced error management in dependable real-time systems. These system-level features include a high priority Low-Latency Peripheral Port (LLPP) for fast peripheral reads and writes, and an Accelerator Coherency Port (ACP) for greater efficiency and more reliable cache coherency with an external data source.

 


The Cortex-R5 Processor

The Cortex-R5 processor, designed for implementation on advanced silicon processes with an emphasis on improved energy efficiency, real-time responsiveness, advanced features and ease of system design. The processor provides a highly flexible and efficient two-cycle local memory interface, enabling SoC designers to minimize system cost and energy consumption.

The Cortex-R5 processor integrates a number of advanced system level features to aid software development and improve reliability in safety and enterprise systems. These include Low Latency Peripheral Ports (LLPP), a coherency interface to enable and keep the Cortex-R5 caches fully synchronized with data being transferred by intelligent peripherals and enhanced ECC support that extends to all of the processor interfaces.

Summary of Cortex-R5 Key Features

  • Fast - high performance 
    • Power-efficient, 8-stage dual issue pipeline with instruction pre-fetch and branch prediction
    • ARMv7R architecture - Thumb-2 / ARM instructions
    • Hardware divide, SIMD, DSP
    • Floating Point Unit (FPU) SP/DP option
    • Harvard I + D caches, 64-bit AMBA AXI-3
  • Advanced technology for real-time system integration
  • Low Latency Peripheral Port (LLPP)
    • Fast access to I/O registers and GIC
    • AMBA AXI-3 I/O with optional AHB
  • Accelerator Coherency Port (ACP)
    • Performance boosting data cache maintenance
    • Micro Snoop Control Unit
  • Enhanced Memory Protect Unit (MPU)
    • 12 or 16 regions. Smaller FPU
  • Extended ECC/parity error management
    • ECC and Parity also on AXI bus port interfaces
  • Dual core configurations
    • For 2x performance (2x 1.66 DMIPS/MHz) or lock-step redundant core for safety critical applications
    • The ACP and µSCU maintains data cache coherency with DMA I/O for both cores
    • Each core has a Low Latency Peripheral Port (LLPP) for deterministic I/O control

Cortex-R5 Performance Power and Area

Processor area, frequency and power consumption are highly dependent on process, libraries and optimizations. The table below estimates a typical single processor implementation of the Cortex-R5 processor on mainstream low power process technology (40nm LP) with high-density, standard-performance cell libraries and 32KB instruction cache and 32KB data cache.

Cortex-R5 Single Processor

40nm LP

Maximum clock frequency Above 600MHz
Performance 1.67 / 2.01 / 2.45 DMIPS/MHz
3.47 CoreMark/MHz
Total area (Including Core+RAM+Routing) From 0.5 mm2
Efficiency From 24 DMIPS/mW

* The first result abides by all of the 'ground rules' laid out in the Dhrystone documentation, the second permits inlining of functions (not just the permitted C string libraries) while the third additionally permits simultaneous multifile complilation. All are with the original (K&R) v2.1 of Dhrystone.



Cortex-R5 Processor

Feature

Description

Microarchitecture Eight-stage pipeline with instruction pre-fetch, branch prediction and selected dual-issue execution. Parallel execution paths for load-store, MAC, shift-ALU, divide and floating point. 1.66 Dhrystone MIPS/MHz. Hardware divider. Binary compatibility with the ARM9, ARM11, Cortex-R4 and Cortex-R7 embedded processors.
Instruction Set ARMv7-R architecture with Thumb®-2 and Thumb. DSP extensions. Optional floating-point unit with single-precision only configuration option.
Cache controllers Harvard memory architecture with optional integrated Instruction and Data cache controllers. Cache sizes configurable from 4 to 64 KB. Cache lines are either write-back or write-through.
Tightly-Coupled Memories Optional Tightly-Coupled Memory interfaces. TCMs are used for highly deterministic or low-latency applications that may not respond well to caching, e.g. instruction code for interrupt service routines and data that requires intense processing. One or two logical TCMs, A and B, can be used for any mix of code and data. TCM size can be up to 8 MB. TCM B has two physical ports, B0 and B1, for interleaving incoming DMA data streams.
Interrupt interface Standard interrupt, IRQ, and non-maskable fast interrupt, FIQ, inputs are provided together with a VIC interrupt controller vector port. The GIC interrupt controller can also be used if more complex priority-based interrupt handling is required. The processor includes low-latency interrupt technology that allows long multi-cycle instructions to interrupted and restarted. Lengthy memory accesses are also deferred in certain circumstances. Worst-case interrupt response can be as low as 20-cycles using the FIQ alone.
Memory Protection Unit Optional MPU configures attributes for either twelve or sixteen regions, each with resolution down to 32 Bytes. Regions can overlap, and the highest numbered region has highest priority.
Floating Point Unit Optional Floating Point Unit (FPU) implements the ARM Vector Floating Point architecture VFPv3 with 16 double-precision registers, compliant with IEEE754. The FPU performance is optimized for single-precision calculations and has (optional) full support for double precision. Operations include add, subtract, multiply, divide, multiply and accumulate, square root, conversions between fixed and floating-point, and floating-point constant instructions.
ECC Optional single-bit error correction and two-bit error detection for cache and/or TCM memories with ECC bits. Single-bit soft errors automatically corrected by the processor. ECC protection possible on all external interfaces.
Parity Optional support for parity bit error detection in caches and/or TCMs.
Master AXI bus 64-bit AMBA® AXI bus master for Level-2 memory and peripheral access.
Slave AXI bus Optional 64-bit AMBA AXI bus slave port allows DMA masters to access the dual-port TCM B interface for high speed streaming of data in and out of the processor.
Low Latency Peripheral Port (LLPP) A dedicated 32-bit AMBA (AXI and optional AHB) port to integrate latency-sensitive peripherals more tightly with the processor.
Accelerator Coherency Port (ACP) A 64-bit AXI slave port to enable for coherency between the processor(s) and external intelligent peripherals such as DMA controllers, Ethernet or Flexray interfaces.
Debug Debug Access Port is provided. Functionality can be extended with DK-R5.
Trace

An interface suitable for connection to CoreSight Embedded Trace Macrocell is present.

Dual core A dual processor configuration for either a redundant Cortex-R5 CPU in lock-step for fault tolerant/fault detecting dependable systems or dual cores running independently, each executing its own program with its own bus interfaces, interrupts etc.

ARM System IP, Development Tools and Physical IP to implement Cortex-R5 processor-based systems.

CoreLink™ and CoreSight™ System IP

NIC-400Configurable hierarchic low latency interconnect for AMBA® 3 AXI™, AHB-Lite and APB components. Configurations can range from a single bridge component, such as an AHB to AXI protocol bridge, to a large infrastructure of 128 masters and 64 slaves in combinations of different AMBA protocols.
QOS-400 Added to NIC-400 to minimize average latency and guarantee worst-case latency and bandwidth of critical interfaces such as DDR memory.
DMC-34x Dynamic memory controllers providing highly efficient interfaces to DRAM by leveraging AMBA AXI interconnect features to optimize memory request scheduling and using built-in Quality of Service controls to manage the initiator's latency and bandwidth requirements. Memory types supported include SDR, DDR, LPDDR (Mobile DDR), eDRAM, DDR2 and LPDDR2 (Mobile DDR2).
SMC-35x Static memory controllers interface AXI interconnects to a range of non-volatile memories with highly configurable parameters. Memory types supported include SRAM, NAND Flash and NOR Flash.
L2C-310 Level-2 cache controller designed to boost performance while reducing overall traffic to system memory and therefore SoC energy consumption. Reducing demands on off-chip memory bandwidth frees up resources for other masters.
DMA-330 A highly flexible micro-programmable Direct Memory Access controller for high-end high-performance energy-efficient AMBA AXI-based processing systems.
PL192 An AMBA AHB advanced Vectored Interrupt Controller (VIC) supporting up to 32 vectored interrupts with programmable priority level and masking.
GIC400 An AMBA AHB and AXI scalable, configurable, low gate count Interrupt Controller that stores vector addresses in memory. Options include multi-processor and TrustZone support.
ETM-R5 The Embedded Trace Macrocell (ETM™) provides real-time instruction and data trace, configured to capture information before and after a specified sequence of events with the processor at full speed.
DK-R5 A complete Debug Kit including ETM-R5 and a fully featured Debug Access Port (DAP) to complement the DAP-Lite shipped with every Cortex-R5. DK components include DAP, cross trigger, ETM, AMBA bus trace, serial wire debug, trace funnel, trace buffer, trace port interface and serial wire viewer.

Development Tools

The ARM Development Suite 5 (DS-5™) tool suite, as well as a wide range of third party tools, operating systems and EDA flows fully support all Cortex-R processors. ARM DS-5 software development tools are unique in their ability to provide solutions that take full advantage of the complete ARM technology portfolio. Tools specific to Cortex-R5 are:

ARM DS-5

ARM Compiler 5.0 with Thumb-2 optimized for Cortex-R5. JTAG debug and ETM trace support.

Fast Models With ARM Fast Models, software development can begin prior to silicon availability. These extensively validated programmer’s view models provide access to ARM-based systems suitable for early software development.
Versatile Express The Versatile™ Express family of development platforms provides the right environment for prototyping the next generation of system-on-chip designs.
Soft Macrocell Model A Soft Macrocell Model (SMM) is an FPGA implementation of an ARM processor, built with ARM development boards

Physical IP

ARM optimized Physical IP platforms for best-in-class implementations of Cortex-R5 on leading semiconductor process technologies.

Standard cell logic libraries AvailaAvailable in a variety of different architectures, ARM Standard Cell Libraries support a wide performance range for all types of SoC designs. Designers can choose between different libraries and optimize their designs for speed, power and/or area.
Memory compilers and registers A broad array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications.
Interface IP A broad portfolio of silicon-proven Interface IP designed to meet varying system architectures and standards. General Purpose I/O, Specialty I/O, High Speed DDR and Serial Interfaces, optimized to deliver high data throughput performance with low pin counts.

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