AMBA Design Tools for CoreLink System IP

AMBA Design Tools for CoreLink System IP Image (View Larger AMBA Design Tools for CoreLink System IP Image)
CoreLinkCoreLink AMBA® design tools from ARM comprise two products, AMBA Designer (ADR-301) for configuring, generating and stitching RTL, and Verification & Performance Exploration (VPE-301) for functional verification and performance optimization of AMBA AXI based System IP and processors.

CoreLink AMBA design tools capture ARM designer knowledge and verification expertise, allowing the system architect to make informed decisions on creating and integrating optimal ARM based solutions for power, performance and area.

AMBA Designer (ADR-301)

  • Making it easy and fast for designers to generate optimal ARM System IP
  • Reducing 3 weeks of manual IP stitching to 3 days

Verification & Performance Exploration (VPE-301)

  • Reducing 2M cycle Mali™200 test bench simulation from 4 hours to 4 minutes
  • Giving a 300x performance boost over conventional functional verification IP

ADR-301 and VPE-301 in the Design Flow

The diagram below shows a design flow where the system architect starts with a spreadsheet analysis of a new or existing design. The further down the design flow, the greater the cost of iterating that phase of development. A combination of ADR-301 and VPE-301 early in the design flow allow more iterations at an earlier stage in the flow.

Once ARM System IP components are generated in ADR-301, VPE-301 provides realistic stimulus for enabling these choices, and reduces risks associated with making intuition-based decisions early on in the design cycle.


AMBA Design Tools Showcase Demonstrations

demo at TechCon3 in October 2009 to illustrate ARMs commitment to building high performance, low power interconnect and memory controller solutions. These developments also combine with the AMBA Interconnect QoS product announcement during the same week.

demo using VPE-301 at ARM DevCon 2008 to explore the performance of a network interconnect design for CPU latency testing. NIC-301  generated two configurations of ADR-301 and the relative performance was compared using VPE-301.


ADR-301 and VPE-301AMBA Designer (ADR-301

Use ADR-301 for selecting, configuring and generating instances of Systems IP from Network Interconnect, through DMA controllers to Memory Controllers.

Once generated, ADR-301 allows the designer to connect each of these blocks together, and to generate a top-level verilog design file. Further, ADR-301 output also includes an industry standard IP-XACT file for integrating into other third party design flows.


Verification & Performance Exploration (VPE-301)

Use VPE-301 to perform functional and performance exploration tasks on your generated block or sub-system.

VPE-301 has the unique ability to monitor not only system performance, but also to capture statistical traffic profiles for replay and even modification.


AMBA Designer (ADR-301)

  • ADR-301 is deployed with every version of AMBA NIC-301 Network Interconnect product
  • ”We saved over 3 weeks engineering effort in configuring and stitching our interconnect components” – Tim Whitfield, Processors Division Engineering Manager, MID platform development 
  • “…easy to hook up various master and slave using ADR-301” – NIC-301 customer

Verification & Performance Exploration (VPE-301)

  • VPE-301 is deployed extensively within the ARM engineering department as well as being available as an external product
  • “VPE-301 animates benchmarking data to bridge the gap between spreadsheet analysis and slow RTL simulation" – Tim Mace, Senior Technical Marketing Manager, Processors Division Fabric Marketing
  • Issue: ”8,000,000 simulation runs required to explore all the design options on a modern DDR2 controller - this is not practical” – Mike Campbell, Technical Lead Processors Division Fabric Engineering
  • Issue: ”I want to determine the cache size on my new design, and I want +500MB/s per second from my memory controller - conventional tools do not help me to easily address this” – Senior System Architect, NA based Semico



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