CoreLink System IP & Design Tools for AMBA

CoreLink System IP & Design Tools for AMBA Image (View Larger CoreLink System IP & Design Tools for AMBA Image)
CoreLink logoCoreLink™ System IP and design tools provide the components and the methodology for designers to build SoCs based on the AMBA® specifications, mazimizing the efficiency of data movement and storage, delivering the performance needed at the lowest power and cost.

The CoreLink 500 series features the CoreLink CCN-504 and CCN-508 cache coherent networks providing up to 1.6 Terabit/s of throughput for full cache coherency between up to sixteen CPUs for the CCN-504 and 32 CPUs for the CCN-508 respectively. They are both paired with the CoreLink DMC-520 Dynamic Memory Controller for DDR3 and DDR4 DRAM interfaces at up to 3200 Mbps x 72-bit. The DMC-520 enhances virtualization support for the ARMv8 architecture based Cortex-A57 and Cortex-A53 processors, with the CoreLink MMU-500 System Memory Management Unit and CoreLink GIC-500 Generic Interrupt Controller.

The CoreLink 400 series features the CoreLink CCI-400 Cache Coherent Interconnect using the AMBA 4 ACE protocol for full cache coherency between up to 8 CPUs, ideal for big.LITTLE processor systems with Cortex-A57 and Cortex-A53 processors or Cortex-A15 and Cortex-A7 processors. The CoreLink NIC-400 Network Interconnect provides a fully configurable heirarchy of sparse cross-bar switches for AMBA AXI4, AMBA AXI3, AMBA AHB and AMBA APB protocols.

The new AMBA 5 CHI specification, specified by ARM with wide cross-industry consultation, is implemented in the CoreLink CCN-504. The AMBA 4 specifications cover five protocols: AMBA ACE, AMBA ACE-Lite, AXI4, AMBA AXI4-Lite and AMBA AXI4-Stream.

For additional information on AMBA Specifications please see the AMBA FAQ Pages.


CoreLink 500 Product Range

The newest and highest performance family of system IP includes the recently announced CoreLink CCN-508 cache coherent network along with the CoreLink CCN-504 cache coherent network and CoreLink DMC-520 dynamic memory controller addresses the challenges of enterprise class SoCs. The ARMv8 architecture is complemented by the CoreLink GIC-500 (GICv3 architecture) and CoreLink MMU-500 (MMUv4 architecture).

CoreLink 400 Product Range

ARM supplies all the major components to move and store data between processors and memory. This includes the recently announced CCI-400 cache coherent interconnect, NIC-400 network interconnect, DMC-400 dynamic memory controller and MMU-400 system memory management unit as well as fully featured cache controllers, DMA controllers, static memory controllers and memory interface PHYs to the highest specifications. AMBA design tools enable the easy configurationperformance exploration and verification of the ARM subsystem.

Tried and Tested IP

High quality ARM CoreLink system IP is widely licensed and implemented by our silicon partners active in many diverse application areas, so you can rest assured that our configurable CoreLink products can be re-used in multiple AMBA-based SoCs over many years.

ARM Expertise in System Design

ARM engineers are world leaders in system design, having delivered a range of highly advanced IP processors  (Cortex-A series, Cortex-R series, Cortex-M series, Mali and Classic ARM processors) and the most deployed interconnect architecture, AMBA. They have the expertise and experience to design and support the CoreLink system IP to maximize system performance and minimize power consumption. ARM engineers also contribute to memory interface specifications in the JEDEC and SPMT standards bodies.

Easy Re-use of IP

AMBA is the most widely used on-chip interconnect architecture in SoC designs providing ready re-use of CoreLink products across all your SoC designs.

Contact your local sales office for more information.


Product Name Key Features
Cache Coherent Network CCN-508            1.6Tb/s cache coherent network for up to 32 CPUs with 1-32MB of L3 cache
Cache Coherent Network CCN-504 1Tb/s cache coherent network for 16 CPUs with 8/16MB of L3 cache
Cache Coherent Interconnect CCI-400 2 fully cache coherent and 3 I/O coherent masters x 3 slaves.
Network Interconnect
+ Quality of Service
+ Virtual Networks
+ Thin Links
AMBA 4 protocol-compliant configurable, hierarchical interconnect.
QoS regulation to manage traffic.
Virtual channels prevent cross-stream and head-of-line blocking.
Thin links reduced wiring.

Dynamic Memory Controller

DMC-520 Highest performance, DDR3/DDR3L/DDR4 memory controller with ECC and RAS
features for designs using the CCN-504.
DMC-400 High bus utilization, multi-channel LPDDR2/DDR3 with QoS and virtual channels.

System Memory Management

MMU-500 Distributed, nested stage 1 & 2 address translation for other
masters and I/O in ARMv8-A and ARMv7-A with Virtualization Extensions
MMU-400 Stage 2 memory translation extends CPU virtualization to other masters.

Generic Interrrupt Controller

GIC-500 Virtualizes interrupts across upto 128 CPUs for Cortex-A57 and Cortex-A53
GIC-400 Virtualizes interrupts across upto 8 CPUs for Cortex-A15 and Cortex-A7

CoreLink™ 500 Series Family

CoreLink CCN-508 and DMC-520

CoreLink CCN-504 and DMC-520


CoreLink 400 Series Family

CoreLink 400 Series block diagram

CoreLink Design Tools for AMBA

Quotes on AMBA from some of our customers:
LSI Logic "To meet the demands of rapidly growing mobile network traffic, LSI and ARM have worked closely to drive a feature-rich on-chip interconnect that can serve as the backbone for industry-leading many-core system-on-chip devices," said Gene Scuteri, vice president of engineering, LSI. "ARM expertise in processor and interconnect technology, guided by LSI's deep understanding of networking and compute workloads, has delivered a robust, carrier-grade interconnect that will deliver scalable, deterministic performance and quality of service for today's most advanced networks."
Calxeda "Calxeda and ARM have been working closely to meet the demands of the datacenter since ARM's initial investment in our company in 2008, and we are beginning to see the fruits that relationship," said Barry Evans, co-founder and CEO, Calxeda. "We are already building our next generation datacenter-class solutions using this new ARM CoreLink CCN-504 technology, and think we will once again send shockwaves across the industry when they are announced."
NEC "Having largely standardized our internal methodology for ARM core-based SoC and macro development around AMBA 2.0 technology we are looking forward to introducing the enhanced capabilities of the AMBA AXI methodology." - Ewald Preiss, manager, Macro Development Group, NEC Electronics (Europe)
 samsung logo "AMBA technology has been very useful in developing our mobile application processors. We believe that the new AMBA AXI methodology would contribute a lot in making the SoC integration more efficient, simpler and easier, definitely with a lot of performance improvement." - Dr. Yun-Tae Lee, vice president of Mobile Solution Project, Samsung Electronics
Toshiba "System-level interconnect can be a bottleneck that erodes performance. One of the reasons ARM CPUs have been so successful in ASIC development is that ARM had the foresight to develop AMBA technology and have energetically deployed it. AMBA technology helps reduce design time for ARM core-based ASICs and is important for the success of the ARM11™ architecture." - Richard Tobias, vice president, ASIC and Foundry Business Unit, System LSI Group, Toshiba America Electronic Components, Inc.
NEC "We believe that the AMBA AXI architecture will enable us to deliver the best solution to our customers." - Tomihiro Ishihara, department manager of SoC design support group, 3rd Custom LSI Division, 1st Business Development Operation Unit, NEC Electronics Corporation.
Atmel "AMBA AXI methodology brings a new step forward for high bandwidth and low latency design with backward AHB compatibility." - Michel Guellec, IP Design manager, Atmel Rousset

Usage of the AMBA trademark is now permitted using the guidlines explained on the ARM Trademarks page.



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