The latest addition the CoreLink GIC-500 Generic Interrupt Controller is designed to support many clusters of Cortex-A57 or Cortex-A53 processors, managing and virtualizing up to 480 shared peripheral interrupt signals between up to 48 CPUs and supports message based interrupts.
The GIC-500 uses affinity level routing for large scalability, GICv3 architecture. This can be consolidated as one monolithic block or as a network of discrete re-distribution blocks to suit size and SoC layout. Message based interrupts may be sent direct to any re-distributor block in the affinity tree.
The CoreLink GIC-400 detects, manages, virtualizes and distributes up to 480 interrupts between up to 8 CPUs in Cortex-A15 and Cortex-A7 multicore clusters. You can configure the GIC-400 to support only the required number of CPUs and interrupts to reduce gate count.
The GIC-400 implements GICv2 Architecture, Security and Virtualization Extensions ARM IHI 0048B.
Find out more...
How to Choose?
|GIC-500||A Generic Interrupt Controller that detects, manages, virtualizes and distributes interrupts using affinity routing between ARMv8 processors (Cortex-A57, Cortex-A53) in multicore clusters. Configurable up to 128 CPUs and 480 shared peripheral interrupts.|
|GIC-400||A Generic Interrupt Controller that detects, manages, virtualizes and distributes interrupts between A-Class processors (Cortex-A15, Cortex-A7) in mutlicore clusters. Configurable up to 8 CPUs and 480 interrupts.|
|GIC-390||An AMBA AXI and AMBA AHB scalable, configurable, low gate count Interrupt Controller which stores the CPU's vector addresses in memory. Configuration parameters include the number of CPU interfaces and interrupts. Options include multi-processor and TrustZone® support.|
|PL190||An AMBA AHB Vectored Interrupt Controller with 32 interrupt sources and 16 vectored addresses.|
|PL192||An AMBA AHB Advanced Vectored Interrupt Controller supports up to 32 vectored interrupts with programmable priority level and masking.|
The CoreLink GIC-500 uses affinity routing for scalable support of message based interrupts.
An example Cortex-A15 system showing GIC-400 interrupt handling.