CoreLink System Memory Management Unit

CoreLink System Memory Management Unit Image (View Larger CoreLink System Memory Management Unit Image)
The CoreLink System MMU provides memory management services to SoC bus masters to complement those provided by the Cortex-A series processor family. Enforcing memory protection and access schema while extending memory virtualization services that match those provided by the main application processor ensures consistent security across the SoC. Providing memory virtualization services in hardware reduces the software interventions needed, minimizing hypervisor overheads and ensuring system performance approaches the optimum.


CoreLink MMU-500

The CoreLink MMU-500 is compatible with the ARMv8-A enabled Cortex™-A57 and Cortex-A53 processors, and is backwards compatible with the ARM Cortex-A15 and ARM Cortex-A7 processors. It offers nested stage 1 and stage 2 accelerated address translation with multiple distributed translation buffers controlled from a single control unit to be compatible with a wide range of bus master types and capabilities. This offers maximum flexibility in implementing efficient SoC designs that need to support virtualized applications.

Customer Quotes:

“The ARM CoreLink MMU-500 System Memory Management Unit enabled APM to quickly integrate an architecturally compliant and proven design into the class leading ARM 64b X-Gene processors allowing our design team to focus on developing differentiated IP. We have been very pleased with the quality of the design and the support provided by ARM.” -Gaurav Singh, VP Technical Strategy, AppliedMicro

CoreLink MMU-400

The CoreLink MMU-400 is compatible with the ARM Cortex-A15 and Cortex-A7 processors and offers stage 2 accelerated address translation for bus masters that already implement MMU functionality for stage 1 translation, such as the Mali-400 Graphics Processor, to reduce the hypervisor overhead in managing complex bus master interactions.

A number of virtualization use cases are outlined in an ARM System MMU Virtualization whitepaper.

CoreLink MMU-400 Performance Specification

Typical TLB hit access latency 2 cycles, miss latency depends on memory sub-system infrastructure .

 Process technology  Frequency  Min     Frequency Max
 CP32LP  400 MHz  533 MHz
 TSMC 40G  400 MHz  800 MHz



CoreLink MMU-500 System Memory Management Unit

ARMv8 translation table format

  • 4kB / 64kB granules @ stage 1 / 2
  • DVMs enhanced
  • Invalidation by IPA
  • XO permission

Larger input address

  • 32 bit VA or 64 bit VA (49 bits)
  • Up to 48 bit IPA (stage 2 only)

Larger output address range

  • Up to 48 bit IPA (stage 1 only)
  • Up to 48 bit PA (stage 2)

Distributed TLBs

  • Point to point connection
  • To increase TLB efficiency and to save power and area
  • Uses n x 1:1 TLB-TCU interface

CoreLink MMU-400 System Memory Management Unit

The MMU-400 provides:

•         Translation of intermediate-physical-address (IPA) to physical-address (PA) – stage 2 translation

•         Multiple transaction contexts that apply to specific streams of transactions

•         Fault handling, logging, and signalling

•         Debug and performance monitoring

 CoreLink System IP products

 Related ARM Products


 CoreLink MMU-500  Cortex-A57, Cortex-A53, Cortex-A15, Cortex-A7 Extends processor virtualization to other bus masters in the system with accelerated stage 1 & 2 address translation in hardware, using local, distributed TLBs.
 CoreLink MMU-400  Cortex-A15, Cortex-A7 Extends processor virtualization to other bus masters in the system with accelerated stage 2 address translation in hardware.

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