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CoreSight for Cortex-R Series Processors

CoreSight for Cortex-R Series Processors Image (View Larger CoreSight for Cortex-R Series Processors Image)
For high performance deeply embedded applications, CoreSight for Cortex-R series processors provides  embedded software developers with all the on-chip debug and real-time trace resources required to develop high quality and optimized embedded products.
 


For many real-time embedded markets - such as mass storage, automotive, printers etc. - being able to observe non-intrusively (without changing the target behavior) how real-time software operates on the target is a key requirement.

Initially introduced for the real-time embedded market, CoreSight CPU Embedded Trace Macrocell (ETM) is a key part of the product development cycle, enabling the large OEM embedded software community to develop high quality, high performance real-time embedded software on ARM architecture.

Building on the ETM success and ARM's experience in real-time trace, CoreSight for Cortex-R series processors provides a complete SoC level debug and real-time trace for embedded applications.


CoreSight for Cortex-R series is a SoC level solution providing control and visibility for high performance deeply embedded applications.

Debug

The CoreSight Debug Access Port is a high performance debug access port enabling external debuggers to access processors and internal system busses such memory buses. The DAP provides a combined debug port supporting traditional JTAG and a high performance 2 pin debug interface (Serial Wire Debug)

DAP mode Number of pins   Nominal frequency
Serial Wire Debug 

2

 > 100Mhz

JTAG

3

 ~ 50Mhz

Trace Macrocells and ETM bandwidth

The CoreSight CPU trace macrocells for Cortex-R , architected to provide highly compressed real-time trace, enabling embedded developers to observe in real-time the software executed on the processors. The main performance characteristics of the CPU trace macrocells are:

Characteristics       Performance 
Trace bandwidth for Cortex-R

Please contact ARM for detailed benchmarks. 

Operating frequency    Same of the processor clock, refer to Cortex-R performance for details. 
Gate Count (NAND2.1 equivalent) CPU trace macrocells are between 10 to 20% of the processor gate count.

CoreSight SoC components, trace port & ETB size

 The CoreSight SoC components provide a complete SoC level debug & trace solution with low silicon and low pin count overhead. All CoreSight SoC component architectures support modern SoC designs as multi power & clock domain and secure SoCs.

Main performance characteristics of the CoreSight SoC components are:

Characteristics  Performance
Operating frequency  400Mhz on 65nm LP (typical)
250Mhz on 90nm
Support for multi clock and power domains
 Gate Count(NAND2.1) equivalent  ~ 40 kGates for a full debug and multicore tracing (TPIU + ETB) 

Trace port size (Trace port interface unit)

By merging all the trace sources in a single trace stream, CoreSight enables to reduce the number of trace ports to only a single port.

The size of the trace port is a function of the trace bandwidth generated by the trace sources and the nature of the trace, some trace sources may produce bursts of data and may create peak bandwidth requiring wider trace port.

For detailed benchmarks on trace port for different processors, please contact ARM.

For reference, benchmarks on Cortex-R4 show that:

  • a 4 bit data trace port running at CPU frequency is in general enough to stream in real-time non-cycle-accurate program trace.
    For a 400Mhz Cortex-R4 system, this means a 4 bits data trace port running at 200Mhz (DDR)
  • a 16 bit data trace port running at CPU frequency is in general enough to stream in real-time full instruction and data trace.
    For a 400Mhz Cortex-R4 system, this means a 16 bit data trace port running at 200Mhz (DDR)

Embedded Trace Buffer (ETB)

When it is not possible to implement a dedicated port (final product, severe IO constraints), trace can be captured on-chip using the CoreSight ETB.
Use of the ETB enables high bandwidth trace capture on the chip. The users based on specific trigger or filter conditions define trace capture.

Please contact ARM for detailed benchmarks.

For reference, for Cortex-R4

  • a 4KB ETB enables to hold trace information for around 25,000 instructions executed.
  • an 8KB ETB can store full program and data trace of around 4,000 instructions executed.

 


CoreSight Design kit for Cortex-R

CoreSight Design Kits consist of the following components:

Component Overview
Debug Access Port Provides debugger access to the cores and buses in a SoC, across multiple power and clock islands, enabling exceptionally high download speeds direct to memory
Embedded Cross Trigger Synchronize debug and trace across multiple cores.
Embedded Trace Macrocell Non-invasively generate cycle-accurate, instruction and data trace of ARM processors running at full speed 
Trace Funnel       Combine multiple trace sources together.
Embedded Trace Buffer Store trace data on-chip at high rates at 32-bit data width, eliminating the need for dedicated trace port pins or an external trace collection unit.  
Trace Port Interface Unit Transmit trace data off-chip via 2-34 pins at frequencies asynchronous to the core. Instrumentation Trace Macrocell for high level, low bandwidth, software generated trace.
Serial Wire Debug High performance 2-pin debug port that replaces the 5/6-pin JTAG interface with multi-drop support.
Serial Wire Viewer  Single pin output for Instrumentation Trace.
Integration Kit     Contain RTL test benches, test vectors and full documentation for easy validation of a designer's own CoreSight subsystem

CoreSight Design Kit for Cortex-R processor family available for licensing:

 CoreSight Design Kit   Compatible with ARM processor  Trace macrocell included 
 CDK-R4      Cortex-R4  ETM-R4

High Speed Serial Trace Port (HSSTP)

The High Speed Serial Trace Port (HSSTP) architecture has been defined by ARM to enable OEMs and silicon providers to standardize on a serial high speed port dedicated to trace.
The HSSTP architecture can be downloaded free of charge from the ARM web site (download HSSTP specification) and is currently supported by several major tool vendors..

For more details on HSSTP please contact ARM.


 

 Processors

Related Products CoreSight Products Benefits
Cortex-R4 CoreSight Design Kit for Cortex-R4 (CDK-R4) Complete debug and real-time trace solution for Cortex-R4 processors.

 

 Tools

Related Products

CoreSight Product features 

Benefits
RealView Development Suite Professional CoreSight ETM-R4, cross-triggering, trace funnels, embedded tace buffers, trace ports, Debug Access Port and Serial Wire Debug. The RealView Debugger supports debug and trace analysis of Cortex-R4 processors including synchronized debug of multiple CPUs.
RealView ICE CoreSight debug infrastructure: Serial Wire Debug, Debug Access Port, cross triggering. Run-control unit with advanced debug functionality over JTAG or Serial Wire Debug connection for debug of single- & multi-core system. Using CoreSight DAP, RVI achieves high speed code download up to 1.45 Mbyte/s.
RealView Trace CoreSight ETM-R4, tace funnels and trace port. The RealView Trace capture unit collects high-speed streaming trace from your target system at up to 32 bits @ 480 MHz trace clock.


 
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