Trace Memory Controller

Trace Memory Controller Image (View Larger Trace Memory Controller Image)
The CoreSight Trace Memory Controller (TMC) enables real-time trace to be used cost effectively during all the product development phases and right up to the point of mass production, giving real-time visibility to all developers including third party software developers.

CoreSight Trace Memory Controller gives cost-effective real-time trace for all development phases

The Trace Memory Controller (TMC) provides a range of trace collection solutions to manage and deliver real-time trace in the most cost effective manner during all product development phases right up to final products.

The TMC supports real-time trace export or capture on-chip as follow:

Usage case
Real-time streaming through the trace port (TPIU)
Export real-time trace through a dedicated trace port.
Provide off-chip and high bandwidth real-time trace for all the SoC trace macrocells.
Real-time streaming through the debug interface (JTAG or 2-pin Serial Wire Debug)
Export real-time low bandwidth system trace.
Enable system level debug & optimization of production silicon in final product for system tuning, failure analysis and maintenance.
Real-time streaming through SoC I/O controllers   Export real-time trace through dedicated or shared I/O controllers.

When implemented with High Speed Serial Trace Port, enables real-time trace export  using Gbit serial ports. When implemented with functional I/O controllers, enables re-use of SoC resources removing the need of dedicated trace ports.

Trace capture on-chip using system memory (several MBytes) MBytes of system memory can be allocated by the s/w & OS for real-time trace.

Remove need for dedicated trace port and enable s/w developers to use as required system memory to debug and optimize their product.

Trace capture using dedicated SRAM (ETB with few KBytes of SRAM) Dedicated SRAM to capture trace.  Provide trace when trace port not available; no intrusion with system memory.

Trace Memory Controller reduces trace overflows and trace port size

The bandwidth generated by SoC trace sources (CPU trace, system trace)  vary over time with an long term average and peaks depending of the code executed and the system instrumentation performed. For many applications, it is not acceptable to lose trace and therefore trace ports have to be over-engineered to support these peaks.

The TMC introduces a new FIFO mode enabling averaging of trace over a long period, reducing risks of overflows (loss of trace) and allowing a smaller trace port, making implementation of trace more cost effective.  Coresight Trace is bursty

TMC configurations

The TMC has three major configurations, fixed when integrated into a system: Embedded Trace Buffer (ETB): Enables trace to be stored in a dedicated SRAM, used as a circular buffer.  This configuration is closest to the classic ETB

  • Embedded Trace FIFO (ETF): Enables trace to be stored in a dedicated SRAM, used either as a circular buffer or as a FIFO. The functionality of this configuration is a superset of the functionality of the ETB configuration.
  • Embedded Trace Router (ETR): Enables trace routing over an AXI interface to system memory or any other AXI slave.

CoreSight TMC

The Trace Memory Controller is an add-on to all CoreSight Design Kits.

It is recommended to use the TMC with the CoreSight System Trace Macrocell to provide system trace visibility at lower cost and for use in end-user products.

On-chip system level visibility with CoreSight - Webinar Document


Find out how to implement the CoreSight System Trace Macrocell in your next generation SoC.  (5Mb PDF)  


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