Steve, emulation product manager on the TI wireless team:
"The System Trace capability utilizes the MIPI System Trace Protocol to provide software developers a hardware-accelerated, multi-core "printf" ability. In a multi-core environment, messages from each core are identified and globally time stamped by hardware. This gives software developers a global, time-correlated view of software execution across cores. But what makes the System Trace truly powerful is when hardware events such as interface performance are added to the System Trace. With the ability to see both software thread execution and hardware performance correlated in time, software developers can quickly find and eliminate any inefficiencies."
System Visibility with CoreSight System Trace
For software, system and hardware engineers, visibility of the complete system is now critical to deliver high performance, power optimized systems in shorter development cycles.
The new ARM CoreSight System Trace Macrocell (STM) extends low-cost real-time visibility of software and hardware execution to all software developers, in particular application and kernel developers, enabling rich, optimized and low power software on ARM processor-powered devices across the whole supply chain.
Low latency, high performance software instrumentation
The STM enables low latency and high bandwidth printf style debug capability that gives developers more visibility into their software without altering the system behavior, making it easier to develop and optimize software on ARM processor-based systems.
The STM delivers:
- Low-latency, high-bandwidth, non-intrusive and time stamped software instrumentation of the kernel and user space, enabling software developers to gain more visibility on how their software execute in their software without altering the behavior of the system,
- An industry standard for instrumentation trace enabling any software running on any master to use this resource
- A scalable solution enabling multi-processors and processes to access STM without being aware of others; STM supports 65,536 channels enabling significant scalability
System performance tuning and debug
To system developers, the STM provides timing-accurate on-chip visibility of the software and hardware interaction, enabling ARM silicon Partners and OEMs to optimize even further their SoCs and bring their platforms to market faster.
An industry standard
The CoreSight System Trace Macrocell offers an industry standard across all markets for system visibility. All major tool vendors will support ARM STM during 2010.
STM complements the industry standard Embedded Trace Macrocell® (ETM®) and is compliant with MIPI® System Trace specification.