Login

CoreSight System Trace Macrocell

CoreSight System Trace Macrocell Image (View Larger CoreSight System Trace Macrocell Image)
The CoreSight™ System Trace Macrocell gives real-time SoC level visibility at affordable cost up to end product.

The System Trace Macrocell enables real-time instrumentation of software without altering system behavior and real-time analysis of the platform behavior and performance.

 

 


Customer Successes

Steve, emulation product manager on the TI wireless team:

"The System Trace capability utilizes the MIPI System Trace Protocol to provide software developers a hardware-accelerated, multi-core "printf" ability. In a multi-core environment, messages from each core are identified and globally time stamped by hardware. This gives software developers a global, time-correlated view of software execution across cores. But what makes the System Trace truly powerful is when hardware events such as interface performance are added to the System Trace. With the ability to see both software thread execution and hardware performance correlated in time, software developers can quickly find and eliminate any inefficiencies."

System Visibility with CoreSight System Trace

For software, system and hardware engineers, visibility of the complete system is now critical to deliver high performance, power optimized systems in shorter development cycles.

The new ARM CoreSight System Trace Macrocell (STM) extends low-cost real-time visibility of software and hardware execution to all software developers, in particular application and kernel developers, enabling rich, optimized and low power software on ARM processor-powered devices across the whole supply chain.

Low latency, high performance software instrumentation

The STM enables low latency and high bandwidth printf style debug capability that gives developers more visibility into their software without altering the system behavior, making it easier to develop and optimize software on ARM processor-based systems.

The STM delivers:

  • Low-latency, high-bandwidth, non-intrusive and time stamped software instrumentation of the kernel and user space, enabling software developers to gain more visibility on how their  software execute in their software without altering the behavior of the system,
  • An industry standard for instrumentation trace enabling any software running on any master to use this resource
  • scalable solution enabling multi-processors and processes to access STM without being aware of others; STM supports 65,536 channels enabling significant scalability

System performance tuning and debug

To system developers, the STM provides timing-accurate on-chip visibility of the software and hardware interaction, enabling ARM silicon Partners and OEMs to optimize even further their SoCs and bring their platforms to market faster.

An industry standard

The CoreSight System Trace Macrocell offers an industry standard across all markets for system visibility. All major tool vendors will support ARM STM during 2010.

STM complements the industry standard Embedded Trace Macrocell® (ETM®) and is compliant with MIPI® System Trace specification.


ARM System Trace for Cortex-A and Cortex-R Processor-based SoC

The CoreSight System Trace Macrocell is architected to provide low latency and high bandwidth real-time system instrumentation required for real-time and application based platforms.

The ARM STM supersedes the Instrumentation Trace Macrocell (ITM) for these applications; for Cortex-M series processor-based devices, ITM remains the preferred solution.

STM Key performance characteristics

  • Designed to operate at system frequency for Cortex-A and Cortex-R processor-based SoC (e.g. at least 400MHz on 65LP)
  • 32-bit data trace path (32-bit AXI interface, 32-bit ATB interface) for high bandwidth and low latency system instrumentation
  • Fully memory-mapped software stimulus supporting 65,536 stimulus ports and 128 masters
  • Compatible with the latest MIPI® System Trace protocol

 


The STM has the following features:
  • 32-bit Advanced eXtensible Interface (AXI) slave interface for extended stimulus port inputs
  • Hardware event observation interface tracing 32 hardware events
  • Direct Memory Access (DMA) peripheral request interface
  • 32-bit debug Advanced Peripheral Bus (APB) slave interface for configuration and status
  • 32-bit Advanced Trace Bus (ATB) master interface for trace output
  • Fully memory-mapped software stimulus supporting 65,536 stimulus ports and 128 masters
  • Full support for guaranteed and invariant timing software stimulus writes
  • Timestamping of trace events.
  • Leading zero data compression
  • Single-shot and multi-shot triggers with a cross-triggering port, trigger packet insertion, and ATB trace triggers
  • Internal and external source for System Trace Protocol version 2 (STPv2) synchronization

CoreSight STM is a CoreSight Design Kit add-on

The CoreSight System Trace Macrocell is an add-on to the CoreSight Design Kits and can be integrated with any CoreSight Design Kits (CoreSight for Cortex-A, CoreSight for Cortex-R, CoreSight for ARM11 and ARM9).

 

CoreSight Trace Memory Controller

The CoreSight Trace Memory Controller complements the System Trace Macrocell and enables effective management of trace during all the life of the product.

In particular, the Trace Memory Controller allows:

  • System trace to be exported through the debug interface (JTAG or Serial Wire Debug) removing the need for extra pins. This addresses need for low bandwidth system visibility in final product.
  • CPU and system trace capture in system memory, allowing trace to be used by more developers.

On-chip system level visibility with CoreSight - Webinar

Listen to the CoreSight on-demand webinar and find out to implement the CoreSight System Trace Macrocell in your next generation SoC.

Download the webinar presentation  

CoreSight System Trace Macrocell and Trace Memory Controller


Maximise


Cookies

We use cookies to give you the best experience on our website. By continuing to use our site you consent to our cookies.

Change Settings

Find out more about the cookies we set