The ARM CoreLink™ NIC-400 Network Interconnect provides a fully configurable, hierarchical, low latency, low power connectivity for AMBA® 4 AXI4™, AMBA 3 AXI3™, AHB™-Lite and APB™ components. The NIC-400 adds new features over the NIC-301 such as advanced power management with heirarchical clock gating and options for Thin Links to reduce routing congestion and QoS Virtual Networks to prevent blocking.
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Configurable by design
- The CoreLink NIC-400 Network Interconnect is a highly configurable IP that can be optimized to suit the requirements of a complex SoC using the AMBA protocols. The QoS-400 Advanced Quality of Service option provides dynamic bandwidth or latency controlled regulators for the efficient and intelligent management of traffic in complex multi-master designs.
- New with the NIC-400 is the QVN-400 QoS Virtual Networks option to prevent cross-stream or head-of-line blocking through a priority driven allocation of buffer space to different virtual channels in both the interconnect and the dynamic memory controller (DMC-400).
- The TLX-400 Thin Links option for NIC-400 packetized AXI4 connections, for transmission between switches over fewer signals to reduce wiring congestion and ease timing closure
Coherency between high performance CPU clusters, GPU and other masters
- The NIC-400 can be used together with the CoreLink CCN-504 Cache Coherent Network or the CoreLink CCI-400 Cache Coherent Interconnect to extend I/O coherency to larger numbers of masters.
Design and build a network of AMBA interconnect switches
A ‘must’ for small geometries and increasing numbers of IP cores
- Each switch can be configured for different bus widths from 32 to 256 bits wide, and for different clock domains with automatic insertion bus width and clock conversion bridging
Optimized for low latency
- The latest release includes new bridges with reduced arbitration & translation latency across clock domains, data widths and AMBA protocols
Advanced timing closure options for high frequency
- The user has full control of register placement allowing fine grain tuning in the trade-off between clock speed and latency
- Timing closure can be aided by per-channel and per-direction timing closure to isolate long paths
Data packing & buffering for efficient communication
- Configurable address and data buffers can be inserted to reduce translation stall
- Up-sizing bridges efficiently pack data when going from narrow to wide data paths
Integrated with AMBA design tools
- New user interface configures a network of interconnect switches, with full control of port types (AXI, AHB and APB), bus width and clock domain selection