The ARM® CoreLink™ CCN-508 Cache Coherent Network extends energy efficiency to enterprise solutions scaling up to 32 processor cores. This gives system architects the flexibility to create optimal solutions for enterprise applications including storage, servers and network infrastructure.
CoreLink CCN-508 includes an integrated Level 3 Cache from 1 to 32 MB. CoreLink CCN-508 offers a high bandwidth interconnect supporting AMBA 5 CHI protocol and bandwidth approaching 1.6 terabits per second.
CoreLink CCN-508 is optimized for the latest ARMv8 64-bit processors including Cortex-A57 and Cortex-A53. CoreLink CCN-508 is part of a series of products offering designers a scalable, cache coherent interconnect for ‘many-core’ networking infrastructure and server solutions.
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Optimized for high-performance enterprise solutions
- The CoreLink CCN-508 enables system coherency targeting mid to high end infrastructure and high-performance computation markets.
- Optimized for compute performance, scaling up to 32 ARMv8 64-bit processors.
- This technology reduces the need to access off-chip memory, saving time and energy, which is a key metric for enterprise customers.
Optimized for ARM Cortex Processors
The CoreLink CCN-508 supports the high performance and efficient cores including the Cortex-A57 and Cortex-A53 processors, and is in the series of ARM CoreLink CCN that support the AMBA 5 CHI standard. This CHI (Coherent Hub Interface) has been developed to support high frequency, non-blocking data transfers between multiple fully coherent processors. It is especially suited for enterprise networking and server applications.
Integrated Low Latency Level 3 Cache
The CoreLink CCN-508 Cache Coherent Network includes an integrated level 3 (L3) cache and snoop filter functions. The L3 cache, which is configurable up to 32MB, extends on-chip caching for demanding workloads and offers low latency on-chip memory for allocation and sharing of data between processors, high-speed IO interfaces and accelerators. The snoop filter removes the need for broadcast coherency messaging, further reducing latency and power.
High Performance DDR3 and DDR4 Memory Interfaces
The CoreLink CCN-508 is optimized to work with the CoreLink DMC-520 Dynamic Memory Controller providing a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. Enterprise class RAS (Reliability, Availability and Serviceability) features such as ECC for x72 DRAM, TrustZone security and end-to-end QoS (Quality of Service) are integral components of this new memory controller.