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VSTREAM Virtual Debug Interface

VSTREAM Virtual Debug Interface Image (View Larger VSTREAM Virtual Debug Interface Image)
VSTREAM is a fast and flexible virtual debug interface that connects software debuggers to hardware assisted verification systems such as Cadence Palladium, Eve ZeBu and Mentor Veloce and RTL simulators like Cadence Incisive, Mentor ModelSim & Questa and Synopsys VCS.  

VSTREAM enables the stop-mode debug features usually available in professional debug adaptors including stopping the processor, view and change the value of processor registers and system memory and single-step through code. However, this is not done via a physical JTAG connection, but via SCE-MI2 or ZEMI-3 transactors directly into the SoC RTL. Not only this virtual connection is much faster, but it is also easier to start remotely, not requiring any modification to the emulator hardware set-up.

It helps to verify the correct implementation of the debug and trace fabric of the SoC, including any CoreSight components, by running high-level test patterns and connecting an actual debugger to the RTL simulator. The connection of the processor to the memory system and memory-mapped peripherals can be easily validated by opening memory views in the debugger.

VSTREAM supports post-process PTM™ and ETM™ instruction trace after a simulation run in order to get a history of instructions executed by the processor in a non-intrusive way.

 


When used in conjunction with VSTREAM, ARM software debuggers such as RVD and DS-5 Debugger provide a responsive graphical debug environment for processors running on verification systems. From the debugger it is possible to stop the processor, view and change the value of processor registers and system memory, and single-step through code. With VSTREAM large software images can be downloaded to memory in a matter of seconds.

VSTREAM enables more efficient software development in the early stages of system design, improving the utilization of hardware emulators and reducing project risk and time-to-market.It also helps in proving the integration of SoC components by running functional test software including boot code on RTL simulators.   

 

VSTREAM client/server architecture


  • Virtual Debug Interface to hardware emulators and RTL simulators
  • Support for all ARM Cortex processors
  • Support for Mentor Veloce, Eve ZeBu and Cadence® Palladium® series emulators
  • Convenient virtual solution with no hardware attached to the emulator
  • Support for Cadence Incisive, Mentor ModelSim & Questa and Synopsys VCS RTL simulators
  • Remote access from the debugger workstation via a TCP/IP connection
  • Code download at speeds of up to 270 KBytes per second
  • Code single-stepping at over 1.5 steps per second

Client host PC requirements

  • Pentium IBM-compatible machine
  • A TCP/IP connection
  • Operating System
    • Windows XP Professional service pack 3 32/64-bit
    • Windows 7 Professional 32/64-bit
    • Windows 7 Enterprise 32/64-bit
    • Red Hat Enterprise Linux 5 Desktop and Workstation option, Standard 32/64-bit

Emulator workstation requirements

  • Pentium IBM-compatible machine
  • A TCP/IP connection
  • Operating System
    • Red Hat Enterprise Linux 5 Desktop and Workstation option, Standard 64-bit

Supported Emulators

  • Mentor Veloce
  • Cadence Palladium III and PXP
  • Eve ZeBu

Supported RTL Simulators

  • Mentor ModelSim and Questa
  • Cadence Incisive
  • Synopsys VCS  

Target interface

  • Direct virtual interface to a CoreSight™ Debug Access Port (DAP) or DAP-Lite
  • Code download at speeds of up to 270 KBytes per second
  • Code single-stepping at over 1.5 steps per second
  • Remote target reset: Yes

Debugger interface

  • Connection protocols:
    • RVI-API (to RVD Debugger)
    • RDDI (to DS-5 and other debuggers)

Processor and target IP support

  • ARM processor series:
  • CoreSight debug and trace components:
    • Debug Access Port (DAP)
    • DAP-Lite
    • Embedded Trace Buffer (ETB)
    • PTM™ and ETM™ Instruction Trace


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