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ARM1136J(F)-S Hardware Design

ARM Training Course

Details on this training course are provided below. Please contact Support for information about booking any of ARM's training courses.



Summary:

This course is designed for those who are designing hardware based around the ARM1136J(F)-S core. Including an introduction to the ARM product range and supporting IP, the course covers the ARM core range and AMBA on-chip bus architecture. The ARM debug architecture, real-time trace solution and simulation models are also covered. The course includes a number of worked examples to reinforce the lecture material.

Prerequisites:

  • Some knowledge of embedded systems.
  • Familiarity with digital logic or hardware / ASIC design issues.
  • A basic awareness of ARM is useful but not essential.

Audience:

Hardware design engineers who need to understand the issues involved when designing SoC's around the ARM1136J(F)-S core.

Length:

4 days

Modules:

  • The ARM Architecture
  • ARM CPU Architectures
  • Memory Sub-systems
  • Memory Management
  • Memory Access Behavior
  • ARM1136 Overview
  • ARM1136 Instruction Sets
  • Exception Handling
  • AHB Protocol
  • AHB Connection Architectures
  • APB
  • ADK
  • Primecell VIC
  • ARM1136 Processor Core
  • ARM1136 L1 Sub-Systems
  • ARM1136 L2 Interfaces
  • ARM1136 Implementation
  • ARM1136 Example System
  • ARM1136 Clocks, Resets & Power Management
  • ARM1136 Memory Management
  • ARM1136 Booting
  • ARM1136 Interrupts
  • ARM1136 Multiprocessor synchronization
  • ARM1136 L2 Caches
  • ARM11 Coprocessors
  • ARM11 Invasive Debug
  • ARM11 Non-Invasive Debug
  • ARM Processor Simulation Models
  • ARM1136 Integration

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