Learn the Architecture - A-profile
Explore more guides for Arm CPU and system architectures.
Learn more about the Arm A-profile CPU architecture.
Architecture Fundamentals
This guide provides a non-technical introduction to the Arm Architecture.
This guide introduces the exception and privilege model in AArch64. It covers Exception Levels - EL0, EL1, EL2, EL3 - synchronous and asynchronous exceptions, including interrupts - Serror, IRQ, FIQ - and virtual exceptions.
This learn the architecture guide introduces the A64 instruction set, which is used in AArch64.
This guide describes the virtualization support in the Armv8-A and Armv9-A AArch64, including basic virtualization theory, stage 2 translation, virtual exceptions, and trapping. It covers Arm nested virtualization, Arm VHE, Secure EL2 and Arm VMID.
This guide introduces the Arm Generic Timer; the timer framework for A-profile PEs.
This book provides an introduction to Arm technology for programmers using Arm Cortex-A series processors conforming to the Armv7-A architecture.
This guide explains extensions to the Arm architecture and provides guidance on how to read and use them. It shows differences between Armv9-A v Armv8-A.
Memory Management and Memory Model
The learn the architecture guide introduces the Arm MMU, which is used to control virtual to physical address translation.
This guide introduces the memory attributes and properties in Armv8-A and Armv9-A.
This guide introduces the memory ordering model that is defined by the Armv8-A and Armv9-A architecture.
Learn more about the Arm Memory Model Tool, explore a working example, and learn how to automatically generate litmus tests.
This guide describes the support for transactional memory introduced in Armv9-A.
Vector and Matrix Processing
This series of guides introduces Neon, shows you how to optimise C code using intrinsics, and how to use your compiler to automatically generate code that contains Armv8-A advanced SIMD instructions.
This guide provides an in-depth description into Scalable Vector Extension (SVE) and Scalable Vector Extension V2 (SVE2), illustrated with extensive code examples. The guide shows software developers how to explain SVE or SVE2 in their software.
The Scalable Matrix Extension (SME) introduced in this guide is an architectural solution by Arm to accelerate matrix operations. This guide describes SME and SME2.
This guide introduces Arm Neon technology, the Advanced SIMD (Single Instruction Multiple Data) architecture extension for implementations of Armv8–A, Armv9-A and Armv8–R.
This guide shows you how to use Arm Neon intrinsics in your C, or C++, code to take advantage of the Advanced SIMD technology in the Armv8-A and Armv9-A architectures.
This guide shows how to use the auto-vectorization features in Arm Compiler 6 and CLANG to automatically generate code that contains Armv8-A and Armv9-A Advanced SIMD instructions.
This guide looks at SVE vs Neon. It describes the differences between the Scalable Vector Extension (SVE) of the Armv8-A and Armv9-A instruction set and the Advanced SIMD architectural extension (Neon). It also describes the coding best practices for both.
This guide introduces the version 2 of the Scalable Vector Extension (SVE2), which is part of the Armv9-A architecture. It describes the extension concept, main features, application domains, and how to develop programs for SVE2.
This guide shows you how to use SVE in your C and C++ code, and how to perform some basic optimizations.
This guide summarizes the important differences between coding for the Scalable Vector Extension (SVE) and coding for Neon. For users who have already ported their applications to Armv8-A Neon hardware, the guide also highlights the key differences to consider when porting an application to SVE.
GIC and SMMU
This guide provides an overview of the Generic Interrupt Controller (GIC), describing the operation of an Arm GICv3 compliant interrupt controller, and providing information about configuration for use in a bare metal environment.
This guide introduces Locality-specific Peripheral Interrupts (LPIs), a type of interrupt introduced in GICv3/v4.
This guide describes the support for virtualization in the GICv3 and GICv4 architecture. It covers the controls available to a hypervisor for generating and managing virtual interrupts.
This guide describes the basic operation of the Arm System Memory Management Unit version 3 (SMMUv3) and use cases of the SMMUv3.
Security
This guide introduces Arm TrustZone architecture, an efficient, system-wide approach to security with hardware-enforced isolation built into the CPU.
This guide examines the features in Armv8-A and Armv9-A that help to mitigate against software attacks, such as ROP and JOP attacks. The guide covers pointer authentication, branch target authentication, and memory tagging.
This guide introduces Memory Tagging Extension (MTE). It shows developers how to use MTE to increase the robustness and security of their software.
This guide explains the principles of confidential computing, and describes how the Arm Confidential Compute Architecture (Arm CCA) enables confidential computing in an Arm compute platform.
This guide introduces the Arm Realm Management Extension (RME) introduced in Armv9-A, a hardware component of the Arm Confidential Compute Architecture.
This guide describes the key software features that the Arm Confidential Compute Architecture introduces or changes to provide an environment for confidential computing.
Debug and Trace
This guide introduces the Armv8-A and Armv9-A debug architecture that is incorporated into the Arm architecture for application class processors.
This guide provides an overview of Armv8-A and Armv9-A external debug, and describes the external debug features that the architecture supports.
This guide introduces the debug and trace infrastructure support that is provided by the Arm CoreSight Architecture.
This guide describes concepts that are useful to know before debugging an Armv8-A processor, including different types of debug, target types and target states.
This guide focuses on characteristics that are common to bare-metal debuggers that target the Armv8-A architecture. It also covers what you need to know when you work with debuggers, and possible consequences of their use.
This guide provides a high-level view of trace in Armv9-A systems, including how trace works and is used.
This blog introduces the concept of using SPE for performance analysis and root cause analysis, targeting software developers, performance analysts, and silicon engineers.
MPAM
This guide introduces the Memory System Resource Partitioning and Monitoring (MPAM), an optional addition to the Arm architecture to support memory system partitioning.
This guide describes the firmware and software that are part of the Memory System Resource Partitioning and Monitoring (MPAM).
This guide covers system-level design considerations for MPAM systems and introduces the management interface found in Arm MPAM IP.
RAS
This guide introduces Reliability, Availability, and Serviceability (RAS), the three key attributes of a robust, dependable, computer system.
Software Development
This guide describes how to create an embedded image, including compiling the program, specifying the memory map, and using a model to run the image.
We're working on a new guide. Until it's ready, you can read our Application Note: Bare-metal Boot Code for Armv8-A Processors.
This blog describes three use cases for the Armv8.4-A dot product instructions, and shows how we used these instructions to improve the performance of the libvpx implementation of VP9.
Books
Arm also provides books on subjects related to Arm architectures and CPUs. You can download copies of these books by registering via the links below.