AMBA 5

AMBA 5 is the latest generation of the freely available AMBA protocol specifications. It introduces the Coherent Hub Interface (CHI) architecture, which defines the interfaces to connect fully coherent processors and high-performance interconnects. AMBA 5 also introduces the AXI5, ACE5 and AHB5 protocols, which extend prior generations to include a number of performances and scalability features, and to align and complement CHI.

Find out more about the major revisions to the AMBA AXI and CHI specifications.

The AMBA Advanced High-performance Bus (AHB) specification defines an interface protocol most widely used with Cortex-M processors, for embedded designs and other low latency SoCs. The AHB5 protocol builds upon the previous generation of AHB-Lite with two key goals:

• To complement the Armv8-M architecture and extend the TrustZone security foundation from the processor to the entire system.
• To provide consistency and alignment with the AMBA 4 AXI specification to:
  • Ease integration of Cortex-A and Cortex-M based systems in a SoC.
  • Allow a unified TrustZone security solution inclusive of AXI and AHB systems.

The new properties introduced in the specification are:

• Secure/Non-secure signaling in address phase to indicate secure or non-secure transactions.
• Extended memory types to support more complex systems.
• Exclusive transfers that support semaphore-type operations.

The AHB5 provides further clarifications of AHB-Lite protocol properties, as they become more widely adopted:

• Multiple subordinate select for area efficiency.
• Single-copy and multi-copy atomicity enabling scaling to multiple cores.
• User signaling allowing for user extensions and consistency with the AMBA 4 AXI specification.

Issue C of the AMBA AHB specification adds new optional features, such as the interface parity protection and write strobes.

AMBA AXI-Stream defines an interface for unidirectional data transfers with greatly reduced signal routing. Key features are:

• Support for single and multiple data streams using the same set of shared wires.
• Support for multiple data widths within the same interconnect.
• Ideal for implementation in FPGA.

Issue B of the AMBA AXI-Stream specification defines the AXI5-Stream and introduces new features, such as the interface parity protection and wake-up signaling.

The AMBA Distributed Translation Interface (DTI) protocol specification aligns with the Arm System MMU architecture, to define a scalable, distributed messaging protocol for translation services. In an SMMU implementation, there are typically three components:

• A Translation Control Unit (TCU) that performs the translation table walks.
• A Translation Buffer Unit (TBU) that intercepts transactions in need of translation and can cache those translations to reduce transaction latency.
• A PCI Express (PCIe) Root Complex that includes Address Translation Services (ATS).

DTI is a point-to-point protocol where each channel consists of a link between a TBU or PCIe Root Port implementing ATS, and a TCU. The specification outlines two different protocols:

• DTI-TBU: Defines communication between a TBU and a TCU.
• DTI-ATS: Defines communication between a PCIe Root Complex and a TCU.

Issue E of the DTI specification introduces the DTI protocol version 2 (DTIv2). DTIv2 includes support for Armv8.2 features, Memory System Resource Partitioning and Monitoring (MPAM) and more outstanding translation requests.

The AMBA Low Power Interface (LPI) specification defines Q-Channel and P-Channel interfaces, designed to manage clock and power features of SoC components. Issue D of the AMBA LPI specification adds new optional features, such as the interface parity protection.