Course aim

To produce students with solid introductory knowledge on VLSI concepts and application of these concepts in simulation, verification, and physical implementation of a simplified microprocessor using standard industry tools.

Learning outcomes

• Knowledge and understanding of
  • The characteristics of the nonideal transistor due to high field effects, channel length modulation, threshold voltage effects and leakage
  • How to estimate the characteristics of CMOS circuits including noise margins, DC response and RC delay models.
  • How to estimate the resistance and capacitance of on-chip wires and describe methods to optimize wire delay, power consumption and crosstalk in on-chip wires.
  • The operation of CMOS latches and flip-flops and plan cell layouts using stick diagrams.
  • The limits imposed by timing constraints such as setup and hold time, propagation and contamination delays in sequential circuits.
  • The importance of testing in chip design and the concepts of stuck-at fault, Automatic Test Pattern Generation, Built in Self Test.
  • The different SRAM architecture.
  • The sources of power dissipation in a circuit and methods to control power losses.
  • The implications of clock distribution networks on skew and clock power consumption.
  • The sources and effects of on-chip variation.
  • How to simulate a circuit using Simulation Program with Integrated Circuit Emphasis (SPICE) to determine its DC transfer characteristics, Transient response and Power consumption.

     

• Intellectual
  • Outline the key characteristics/features of nMOS and pMOS transistors and draw the cross section of a CMOS inverter.
  • Use plots and cross section diagrams to describe the current and voltage (I-V) characteristics of the MOS device when operating in cut off, linear and saturation regions.
  • Describe the effects of technology scaling on the number and cost of transistors power dissipation in devices.
  • Explain logical effort and show how it can be applied in minimizing the delay of a combinational circuit path.
  • Explain and demonstrate techniques used to optimize combinational logic circuits for best critical paths and best delay/power trade-offs for logic gates.
  • Describe and explain the features of different adder architectures including: Carry-Ripple Adder, Carry-Skip Adder, Carry-Lookahead Adder, Carry-Select Adder, Carry-Increment Adder and Tree Adder.
  • Design and describe the operation of data path circuits such as comparators, shifters, multi-input adders and multipliers.
  • Describe the operation of Electrostatic discharge (ESD) protection circuits using their circuit diagram.
  • Describe the implementation of a simplified processor at abstraction levels including: Architecture, Microarchitecture, Logic Design, Circuit Design, Physical Design, Verification & Test.

     

• Practical
  • Design, implement, simulate, and verify simple logic gates from transistor level schematic to layout.
  • Use NC-Verilog to simulate and verify the operation of logic blocks.
  • Use design compiler to synthesize logic gates from hardware description language and use SOC Encounter to place and route logic design.
  • Assemble a chip from schematic, layout, add pad frame and then tape out in GDSII format.

Syllabus