A-Profile Architectures

Decades of Investment in Performance and Security

Each iteration of the Arm A-profile CPU architecture has given developers new and improved tools to build cutting edge AI applications. With features that facilitate machine learning and security stemming from Armv7, our architecture has continued to mature in line with future market needs.

Armv9-A is no exception, enabling faster compute of large datasets, comprehensive security features that protect applications and their data, incredible power efficiency, and data-led software optimization.

Armv9-A

Armv9-A architecture gives developers the programming tools and environment to innovate at pace for the rapidly expanding AI market. It enables faster compute in high-performance use cases, while adding a suite of security features that guarantee data and operation integrity on a device or server. These benefits are delivered without compromising the balance of power consumption and performance inherent in Arm products.

Specifically, Armv9-A is a set of extensions to the Armv8-A architecture, and part of a rolling program of substantial enhancements being deployed over the next few years. The latest implementation is Armv9.4-A. This version contains performance features that accelerate the processing of large datasets, improve bandwidth, and optimize software performance. Armv9.4-A also includes security features that isolate applications from attacks, prevent memory safety issues, and prevent existing code from being used to create a malicious program.

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Armv8-A

The Armv8-A architecture introduces the ability to use 64-bit and 32-bit Execution states, known as AArch64 and AArch32 respectively. The AArch64 Execution state supports the A64 instruction set. It holds addresses in 64-bit registers and allows instructions in the base instruction set to use 64-bit registers for their processing.

The AArch32 Execution state is a 32-bit Execution state that preserves backwards compatibility with the Armv7-A architecture, enhancing that profile so that it can support some features included in the AArch64 state. It supports the T32 and A32 instruction sets.

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