Highly Scalable Mesh for Large Core Count Automotive Designs Including Chiplets
The Arm Neoverse CMN S3AE coherent mesh network is designed to enable scalable performance for automotive applications, central compute, and machine learning (ML) workloads. The highly scalable mesh is optimized for Armv9.2, Armv9, Armv8-A processors, multichip configurations, and CXL attached devices. It forms the foundation for both SoCs and chiplets. It can be customized across a wide range of performance points.
Features and Benefits
The scalable mesh network can be customized to meet system performance and area requirements. The native AMBA 5 CHI network provides high-frequency, non-blocking data transfers between compute, accelerator, and IO to shared memory resources.
CMN S3AE is designed to enable ASIL B use cases, with a range of safety features including ECC & parity mechanisms and other techniques to achieve diagnostic coverage goals.
CMN S3AE forms the foundation for chiplet-based designs. Enabling the key chiplet capabilities needed for next-generation chiplet applications. CMN S3AE enables chiplet designs with same as ease and performance as monolithic designs.
Where Innovation and Ideas Come to Life
Autonomous Vehicles and ADAS
Arm Neoverse V3AE can meet the performance requirements of future autonomous vehicles and advanced driver-assistance systems. The dedicated AE features in Neoverse V3AE, coupled with a safety island that can provide a pathway to the safety requirements for many automotive applications.
Artificial Intelligence (AI)
AI workloads and use cases, and ML, are expanding and defining more applications than ever. This is especially true for the next generation of software-defined vehicles, which is redefining the driving experience. Arm Neoverse V3AE provides new architectural features to enhance ML/AI capabilities for new vehicle applications.
Explore Products and Technologies
Neoverse V3AE
First Armv9.2 Neoverse CPU with safety enhancements for automotive markets. Highest single-thread performance for AI/ML workloads and automotive markets.
Cortex-A720AE
The first Armv9A high-performance Cortex-A CPU based on Arm DynamIQ technology and designed for safety critical applications. Designed for the next generation of software defined vehicles.
Cortex-A520AE
High-efficiency Armv9.2 Cortex-A CPU for safety-critical applications, bringing power efficiency in the smallest silicon footprint. Designed for the next generation of software defined vehicles (SDVs).
A Foundation of Silicon Success
Arm Confidential Computing Architecture
The Arm Confidential Computing Architecture enables memory encrypted VMs, keeping data private and secure from the host platform.
AMBA Coherent Hub Interface Chip-to-Chip (AMBA CHI C2C)
AMBA CHI C2C is an extension to CHI. It defines how the on-chip CHI protocol is packetized for transport over a chip(let)-to-chip(let) link.
CMN S3AE Resources
- Arm’s Broadest Ever Automotive Enhanced IP Portfolio Designed for the Future of Computing in Vehicles
- Virtual Platforms from Arm and Partners Available Now to Accelerate and Transform Automotive Development
- Ecosystem Collaborations Bring Full Stack Software Solutions to Develop Leading-edge Automotive Applications From Day One
- Functional Safety Compute for the Software-defined Vehicle
- Neoverse S3 System IP: A Foundation for Confidential Compute and Multi-chiplet Infrastructure SoCs
- Ecosystem Collaboration Drives New AMBA Specification for Chiplets